8. TIMING CHART
(1) Hole signal input
H0
H1
H2
µPD16882
(2) CMP signal (FGsel: GND, single-phase mode (IND1), FGsel: VDD, 3-phase synthesized mode (IND2))
CMP0
CMP1
CMP2
IND1
IND2
(3) Selection of output MOSFET drive and comparator
Q1
Q2
Q3 (SW)
Q4 SW
Q5 ON
Q6
(SW)
SW
ON
(SW)
SW
ON
ON
(SW)
SW
ON
(SW)
SW
ON
(SW)
SW
(SW)
SW
ON
(SW)
SW
ON
(SW)
SW
ON
ON
(SW)
SW
ON
(SW)
SW
ON
(SW)
SW
(SW)
SW
ON
Data Sheet S13966EJ1V0DS
11