UJA1069 데이터 시트보기 (PDF) - NXP Semiconductors.

부품명

상세내역

일치하는 목록

UJA1069

LIN fail-safe system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

The following operations are possible from Standby mode:

• Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the

microcontroller is triggered periodically and checked for the correct response)

• Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;

the SBC provides information about the reset source to allow different start

sequences after reset)

• Wake-up by activity on the LIN-bus via an interrupt signal to the microcontroller

• Wake-up by bus activity on the LIN-bus via a reset signal

• Wake-up by increasing the microcontroller supply current without a reset signal

(where a stable supply is needed for the microcontroller RAM contents to remain valid

and wake-up from an external application not connected to the SBC)

• Wake-up by increasing the microcontroller supply current with a reset signal

• Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller

• Wake-up due to a falling edge at pin WAKE forcing a reset signal

6.2.6 Sleep mode

In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled

external supplies are switched off entirely, resulting in minimum system power

consumption. In this mode, the watchdog runs in Time-out mode or is completely off.

Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any

operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is

disabled. It is also possible for V3 to be ON, OFF or in Cyclic mode to supply external

wake-up switches.

If the watchdog is not disabled in software, it will continue to run and force a system reset

upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1

becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode.

Depending on the application, the following operations can be selected from Sleep mode:

• Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed

periodically, the SBC provides information about the reset source to allow different

start sequences after reset

• Wake-up by activity on the LIN-bus or falling edge at pin WAKE

• An overload on V3, only if V3 is in a cyclic or in continuously ON mode

6.2.7 Flash mode

Flash mode can only be entered from Normal mode by entering a specific Flash mode

entry sequence. This fail-safe control sequence comprises three consecutive write

accesses to the Mode register, within the legal windows of the watchdog, using the

operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the

SBC will enter Start-up mode and perform a system reset with the related reset source

information (bits RSS[3:0] = 0110).

UJA1069_4

Product data sheet

Rev. 04 — 28 October 2009

© NXP B.V. 2009. All rights reserved.

11 of 64

Share Link: