UJA1065 데이터 시트보기 (PDF) - NXP Semiconductors.

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UJA1065

High-speed CAN/LIN fail-safe system basis chip

NXP Semiconductors. 

NXP Semiconductors

5. Pinning information

5.1 Pinning

UJA1065

High-speed CAN/LIN fail-safe system basis chip

n.c. 1

n.c. 2

TXDL 3

V1 4

RXDL 5

RSTN 6

INTN 7

EN 8

SDI 9

SDO 10

SCK 11

SCS 12

TXDC 13

RXDC 14

n.c. 15

TEST 16

Fig 2. Pin configuration

UJA1065TW

32 BAT42

31 SENSE

30 V3

29 SYSINH

28 n.c.

27 BAT14

26 RTLIN

25 LIN

24 SPLIT

23 GND

22 CANL

21 CANH

20 V2

19 n.c.

18 WAKE

17 INH/LIMP

001aac306

5.2 Pin description

UJA1065_7

Product data sheet

Table 2.

Symbol

n.c.

n.c.

TXDL

V1

RXDL

RSTN

INTN

EN

SDI

SDO

SCK

SCS

TXDC

RXDC

n.c.

TEST

Pin description

Pin Description

1 not connected

2 not connected

3 LIN transmit data input (LOW for dominant, HIGH for recessive)

4 voltage regulator output for the microcontroller (3.3 V or 5 V depending on the

SBC version)

5 LIN receive data output (LOW when dominant, HIGH when recessive)

6 reset output to microcontroller (active LOW; will detect clamping situations)

7 interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to

other ECU interrupt outputs)

8 enable output (active HIGH; push-pull, LOW with every reset/watchdog

overflow)

9 SPI data input

10 SPI data output (floating when pin SCS is HIGH)

11 SPI clock input

12 SPI chip select input (active LOW)

13 CAN transmit data input (LOW for dominant; HIGH for recessive)

14 CAN receive data output (LOW when dominant; HIGH when recessive)

15 not connected

16 test pin (should be connected to ground in application)

Rev. 07 — 25 February 2010

© NXP B.V. 2010. All rights reserved.

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