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UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6. Functional description

6.1 Introduction

The UJA1061 combines all peripheral functions around a microcontroller within typical

automotive networking applications into one dedicated chip. The functions are as follows:

• Power supply for the microcontroller

• Power supply for the CAN transceiver

• Switched BAT42 output

• System reset

• Watchdog with Window mode and Time-out mode

• On-chip oscillator

• Fault-tolerant CAN and LIN transceivers for serial communication; suitable for 12 V

and 42 V applications

• SPI control interface

• Local wake-up input

• Inhibit or limp-home output

• System inhibit output port

• Compatibility with 42 V power supply systems

• Fail-safe behavior

6.2 Fail-safe system controller

The fail-safe system controller is the core of the UJA1061 and is supervised by a

watchdog timer that is clocked directly by the dedicated on-chip oscillator. The system

controller manages the register configuration and controls all internal functions of the

SBC. Detailed device status information is collected and presented to the microcontroller.

The system controller also provides the reset and interrupt signals.

The fail-safe system controller is a state machine. The different operating modes and the

transitions between these modes are illustrated in Figure 3. The following sections give

further details about the SBC operating modes.

UJA1061_6

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 06 — 9 March 2010

© NXP B.V. 2010. All rights reserved.

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