IW4017BN 데이터 시트보기 (PDF) - Integral Corp.
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IW4017BN Datasheet PDF : 6 Pages
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TECHNICAL DATA
IW4017B
Counter/Divider
High-Voltage Silicon-Gate CMOS
The IW4017B is 5-stage Johnson counter having 10 decoded
outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT
signal. Schmitt trigger action in the CLOCK input circuit provides
pulse shaping that allows unlimited clock input pulse rise and fall
times.
The counter is advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low. Counter advancement
via the clock line is inhibited when the CLOCK INHIBIT signal is
high. A high RESET signal clears the counter to its zero count. Use of
the Johnson counter configuration permits high-speed operation, 2-
input decode-gating and spike-free decoded outputs. Anti-lock gating
is provided, thus assuring proper counting sequence. The decoded
outputs are normally low and go high only at their respective decoded
time slot. Each decoded output remains high for one full clock cycle. A
CARRY-OUT signal completes one cycle every 10 clock input cycles
in the IW4017B.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4017BN Plastic
IW4017BDW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
Clock
L
X
X
FUNCTION TABLE
Clock Reset Output State *
Enable
X
L no change
H
L no change
X
H reset counter
Q0=H, Q1-Q9=L,
C0=H
L
L Advance to next
state
X
L no change
X
L no change
H
L Advance to next
state
* Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H
Carry Out = L otherwise, X=don’t care
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