1400 데이터 시트보기 (PDF) - Linear Technology

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1400

Complete SO-8, 12-Bit, 400ksps ADC with Shutdown

Linear Technology 

LTC1400

PI FU CTIO S

VCC (Pin 1): Positive Supply, 5V. Bypass to GND (10μF

tantalum in parallel with 0.1μF ceramic).

AIN (Pin 2): Analog Input. 0V to 4.096V (Unipolar), ±2.048V

(Bipolar).

VREF (Pin 3): 2.42V Reference Output. Bypass to GND

(10μF tantalum in parallel with 0.1μF ceramic).

GND (Pin 4): Ground. GND should be tied directly to an

analog ground plane.

DOUT (Pin 5): The A/D conversion result is shifted out

from this pin.

W

FU CTIO AL BLOCK DIAGRA

CLK (Pin 6): Clock. This clock synchronizes the serial data

transfer. A minimum CLK pulse of 50ns will cause the ADC

to wake up from Nap or Sleep mode.

CONV (Pin 7): Conversion Start Signal. This active high

signal starts a conversion on its rising edge. Keeping CLK

low and pulsing CONV two/four times will put the ADC

into Nap/Sleep mode.

VSS (Pin 8): Negative Supply. –5V for bipolar operation.

Bypass to GND with 0.1μF ceramic. VSS should be tied to

GND for unipolar operation.

AIN

VREF

2.42V REF

CSAMPLE

ZEROING SWITCH

VCC

GND

VSS

12-BIT CAPACITIVE DAC

COMP

CLK

CONV

CONTROL

LOGIC

12

SUCCESSIVE APPROXIMATION

REGISTER/PARALLEL TO

SERIAL CONVERTER

DOUT

1400 BD01

TEST CIRCUITS

DOUT

3k

CLOAD

Hi-Z TO VOH

VOL TO VOH

VOH TO Hi-Z

6

DOUT

5V

3k

CLOAD

Hi-Z TO VOL

VOH TO VOL

VOL TO Hi-Z

1400 TC01

1400fa

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