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AD674BBRZ

Complete 12-Bit A/D Converters

Analog Devices

AD674BBRZ Datasheet PDF : 12 Pages

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AD674B/AD774B

CIRCUIT OPERATION

The AD674B and AD774B are complete 12-bit monolithic A/D

converters that require no external components to provide the

complete successive-approximation analog-to-digital conversion

function. A block diagram is shown in Figure 5.

5V SUPPLY

VLOGIC 1

DATA MODE SELECT

12/8 2

CHIP SELECT

CS 3

BYTE ADDRESS/

SHORT CYCLE A0 4

READ/CONVERT R/C 5

CHIP ENABLE

CE 6

12V/15V SUPPLY

VCC 7

10V REFERENCE

REF OUT 8

ANALOG COMMON

REFERENCE INPUT

REF IN

–12V/–15V SUPPLY

VEE 11

BIPOLAR OFFSET

BIPOFF

10V SPAN INPUT

10VIN 13

20V SPAN INPUT

20VIN

CONTROL

CLOCK

SAR 12

10V

REF

– COMP

I DAC

MSB

199.95

k⍀

I REF

–

DAC

N VEE

LSB

VOLTAGE

DIVIDER AD674B/AD774B

28 STATUS

STS

27 DB11 (MSB)

26 DB10

25 DB9

24 DB8

23 DB7

22 DB6

21 DB5

20 DB4

19 DB3

18 DB2

17 DB1

16 DB0 (LSB)

DIGITAL

COMMON DC

DIGITAL

DATA

OUTPUTS

Figure 5. Block Diagram of AD674B and AD774B

When the control section is commanded to initiate a conversion

(as described later) it enables the clock and resets the

successive-approximation register (SAR) to all zeroes. Once a

conversion cycle has begun, it cannot be stopped or restarted

and data is not available from the output buffers. The SAR,

timed by the clock, will sequence through the conversion cycle

and return an end-of-convert flag to the control section. The

control section will then disable the clock, bring the output

status flag low, and enable control functions to allow data read

by external command.

During the conversion cycle, the internal 12-bit current output

DAC is sequenced by the SAR from the most significant bit

(MSB) to least significant bit (LSB) to provide an output cur-

rent that accurately balances the input signal current through

the divider network. The comparator determines whether the

addition of each successively weighted bit current causes the

DAC current sum to be greater or less than the input current; if

the sum is less, the bit is left on; if more, the bit is turned off.

After testing all the bits, the SAR contains a 12-bit binary code

that accurately represents the input signal to within ± 1/2 LSB.

The temperature-compensated reference provides the primary

voltage reference to the DAC and guarantees excellent stability

with both time and temperature. The reference is trimmed to

10.00 V ± 1%; it can supply up to 2.0 mA to an external load in

addition to the requirements of the reference input resistor

(0.5 mA) and bipolar offset resistor (0.5 mA). Any external load

on the reference must remain constant during conversion. The

thin-film application resistors are trimmed to match the full-

scale output current of the DAC. The input divider network

provides a 10 V or 20 V input range. The bipolar offset resistor

is grounded for unipolar operation and connected to the 10 V

reference for bipolar operation.

DRIVING THE ANALOG INPUT

The AD674B and AD774B are successive-approximation analog-

to-digital converters. During the conversion cycle, the ADC input

current is modulated by the DAC test current at approximately

a 1 MHz rate. Thus it is important to recognize that the signal

source driving the ADC must be capable of holding a constant

output voltage under dynamically changing load conditions.

FEEDBACK TO AMPLIFIER

V+

CURRENT

LIMITING

RESISTORS

RIN

IIN IS MODULATED BY

CHANGES IN TEST CURRENT.

AMPLIFIER PULSE LOAD

RESPONSE LIMITED BY

V– OPEN-LOOP OUTPUT IMPEDANCE.

ANALOG COMMON

IDIFF

ADC

IIN

ITEST

CURRENT

OUTPUT

DAC

COMPARATOR

SAR

Figure 6. Op Amp—ADC Interface

The closed-loop output impedance of an op amp is equal to the

open-loop output impedance (usually a few hundred ohms)

divided by the loop gain at the frequency of interest. It is often

assumed that the loop gain of a follower-connected op amp is

sufficiently high to reduce the closed-loop output impedance to

a negligibly small value, particularly if the signal is low fre-

quency. However, the amplifier driving the ADC must either

have sufficient loop gain at 1 MHz to reduce the closed-loop

output impedance to a low value or have low open-loop output

impedance. This can be accomplished by using a wideband op

amp, such as the AD711.

If a sample-hold amplifier is required, the monolithic AD585 or

AD781 is recommended, with the output buffer driving the

AD674B or AD774B input directly. A better alternative is the

AD1674, which is a 10 µs sampling ADC in the same pinout as the

AD574A, AD674A, or AD774B and is functionally equivalent.

SUPPLY DECOUPLING AND LAYOUT

CONSIDERATION

It is critical that the power supplies be filtered, well regulated,

and free from high-frequency noise. Use of noisy supplies will

cause unstable output codes. Switching power supplies is not

recommended for circuits attempting to achieve 12-bit accuracy

unless great care is used in filtering any switching spikes present

in the output. Few millivolts of noise represent several counts of

error in a 12-bit ADC.

Decoupling capacitors should be used on all power supply pins;

the 5 V supply decoupling capacitor should be connected directly

from Pin 1 to Pin 15 (digital common) and the +VCC and –VEE

pins should be decoupled directly to analog common (Pin 9). A

suitable decoupling capacitor is a 4.7 µF tantalum type in paral-

lel with a 0.1 µF ceramic disc type.

REV. C

–7–

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