AD674BTE 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD674BTE Datasheet PDF : 12 Pages
| |||
AD674B/AD774B
DIGITAL SPECIFICATIONS (For all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%, VLOGIC = +5 V ؎ 10%,
VEE = –15 V ؎ 10% or –12 V ؎ 5%, unless otherwise noted.)
Parameter
Test Conditions
Min
Max
Unit
LOGIC INPUTS
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
–0.5
IIH
High Level Input Current
VIN = VLOGIC
–10
IIL
Low Level Input Current
VIN = 0 V
–10
CIN
Input Capacitance
VLOGIC + 0.5
V
+0.8
V
+10
µA
+10
µA
10
pF
LOGIC OUTPUTS
VOH
High Level Output Voltage
IOH = 0.5 mA
2.4
VOL
Low Level Output Voltage
IOL = 1.6 mA
IOZ
High-Z Leakage Current
VIN = 0 to VLOGIC
–10
COZ
High-Z Output Capacitance
V
0.4
V
+10
µA
10
pF
SWITCHING SPECIFICATIONS (For all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%,
VLOGIC = +5 V ؎ 10%, VEE = –15 V ؎ 10% or –12 V ؎ 5%, unless otherwise noted.)
CONVERTER START TIMING (Figure 1)
Parameter
J, K, A, B Grades T Grade
Symbol Min Typ Max Min Typ Max Unit
Conversion Time
8-Bit Cycle (AD674B) tC
12-Bit Cycle (AD674B) tC
8-Bit Cycle (AD774B) tC
12-Bit Cycle (AD774B) tC
STS Delay from CE
tDSC
CE Pulsewidth
tHEC
CS to CE Setup
tSSC
CS Low During CE High tHSC
R/C to CE Setup
tSRC
R/C LOW During CE High tHRC
A0 to CE Setup
tSAC
A0 Valid During CE High tHAC
6 8 10 6 8 10 µs
9 12 15 9 12 15 µs
4 5 6 4 5 6 µs
6 7.3 8 6 7.3 8 µs
200
225 ns
50
50
ns
50
50
ns
50
50
ns
50
50
ns
50
50
ns
0
0
ns
50
50
ns
READ TIMING—FULL CONTROL MODE (Figure 2)
Parameter
J, K, A, B Grades T Grade
Symbol Min Typ Max Min Typ Max Unit
Access Time
CL = 100 pF
tDD1
Data Valid After CE Low tHD
Output Float Delay
tHL5
CS to CE Setup
tSSR
R/C to CE Setup
tSRR
A0 to CE Setup
tSAR
CS Valid After CE Low tHSR
R/C High After CE Low tHRR
A0 Valid After CE Low
tHAR
75 150
75 150 ns
252
252
ns
203
154
ns
150
150 ns
50
50
ns
0
0
ns
50
50
ns
0
0
ns
0
0
ns
50
50
ns
NOTES
1tDD is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
20°C to TMAX.
3At –40°C.
4At –55°C.
5tHL is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at TMIN, 25°C, and TMAX. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.
REV. C
–3–
CE
tHEC
CS
tSSC
tHSC
tSRC tHRC
R/C
A0
tHAC
tSAC
STS
DB11 – DB0
tDSC
tC
HIGH
IMPEDANCE
Figure 1. Convert Start Timing
CE
tSSR
CS
tHSR
R/C
tSRR
tHRR
A0
tSAR
tHAR
STS
DB11 – DB0
tHD
HIGH
IMPEDANCE
tDD
DATA
VALID
tHL
Figure 2. Read Cycle Timing
5V
HIGH
IMPEDANCE
DBN
3k⍀
100pF
DBN
3k⍀
100pF
HIGH-Z TO LOGIC 1
High-Z to Logic 1
HIGH-Z TO LOGIC 0
High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
5V
DBN
3k⍀
100pF
DBN
3k⍀
100pF
LOGIC 1 TO HIGH-Z
LOGIC 0 TO HIGH-Z
Logic 1 to High-Z
Logic 0 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test
Share Link: 