TSC87C51-12CA 데이터 시트보기 (PDF) - Temic Semiconductors

부품명

상세내역

일치하는 목록

TSC87C51-12CA

Introduction to TSC87C51/C52 OTP Microcontrollers

Temic Semiconductors 

Glossary

TSC87C51/52

Power off Flag

This flag is used by the software to make the difference between a power on reset and a reset exiting from power down.

In the power down mode, the crystal is stopped and the microcontroller power consumption is closed to zero. This flag

is useful for low power application using the power down mode.

Enhanced Timer 2

Two new features are added to the timer 2 :

D Configuration as an up/down counter

D Clock out generation

UART : Automatic Address Recognition

Two new features are added to the UART. These features lower the software task during multi mode operation :

D Automatic Address Recognition ; in this mode the address recognition is done by hardware rather than by software.

D Framing error Detection; a new bit warn the software that one stop bit is missing.

Power–Down output using external interrupt

With this feature an external interrupt can cause a recover from power down mode ; otherwise, only a reset can restart

the microcontroller. this feature provides more flexibility for low power systems.

ALE disabling

The “Address Latch Enable” is activated at a constant rate of 1/6 the oscillator frequency, except during an external data

memory access at which one ALE pulse is skipped. When no external RAM and ROM access is required, the ALE is not

necessary and can generated noise and EMI. With the ALE disable, this signal is only generated under software when

it is required.

ONCE mode

The ON–Circuit Emulation (ONCE) mode facilitates testing and debugging of the system using the microcontroller

without having to remove the device from the circuit. In this mode, the device is placed on an inactive state and an

emulator or test CPU can be used to drive the circuit.

EPROM lock bits

The program lock bits protect the program memory from software piracy.

Four levels interrupt priority

The initial 8051 architecture has two levels interrupt priority. A second Interrupt Priority register has been added,

increasing the number of priority levels to four. This feature provides more flexibility to real time systems.

Full Static Design

This allows to reduce the system power consumption by bringing the clock frequency down to any value, even 0 Mhz

(DC), without loss of data.

MATRA MHS

5

Rev. A – 10 September 1997

Share Link: