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HSP45314(2000) 데이터 시트보기 (PDF) - Intersil

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HSP45314
(Rev.:2000)
Intersil
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HSP45314 Datasheet PDF : 14 Pages
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HSP45314
Electrical Specifications
ATAVD=D25=oDCVfDorDA=ll
+5V (unless otherwise noted),
Typical Values (Continued)
VREF
=
Internal
1.2V,
IOUTFS
=
20mA,
PARAMETER
TEST CONDITIONS
HSP45314
TA = -40oC TO 85oC
MIN TYP MAX
TIMING CHARACTERISTICS
Maximum Clock Rate, fCLK
Maximum Clock Rate, fCLK
CLK Pulse Width, tCW
Maximum Parallel Write Rate
+5V DVDD, +5V AVDD (Note 3)
+3.3V DVDD, +5V AVDD (Note 3)
CLK (Note 3)
Rate of WR
125
-
-
100
-
-
5
-
-
50
-
-
WR Pulse Width, tWW
Data Setup Time, tDS
Data Hold Time, tDH
Address Setup Time, tAS
Address Hold Time, tAH
UPDATE Pulse Width, tUW
UPDATE Setup Time, tUS
UPDATE Hold Time, tUH
UPDATE Latency, tUL
(Note 3)
5
-
-
Between DATA and WR (Note 3)
10
-
-
Between DATA and WR (Note 3)
0
-
-
Between ADDR and WR (Note 3)
12
-
-
Between ADDR and WR (Note 3)
0
-
-
(Note 3)
5
-
-
Between UPDATE and CLK (Note 3)
2
-
-
Between UPDATE and CLK (Note 3)
4
-
-
After UPDATE, before analog output change, if asserted after
writing to the control registers
-
14
-
UPDATE Latency, tUL
After UPDATE, before analog output change, if asserted before
-
11
-
writing to the control registers
Phase Pulse Width, tPW
Phase Setup Time, tPS
Phase Hold Time, tPH
Phase Latency, tPL
PH(1:0) (Note 3)
Between PH(1:0) change and CLK (Note 3)
Between PH(1:0) change and CLK (Note 3)
Between PH(1:0) change and analog output change
5
-
-
2
-
-
4
-
-
-
12
-
ENOFR Pulse Width, tEW
ENOFR Setup Time, tES
ENOFR Hold Time, tEH
ENOFR Latency, tEL
ENOFR (Note 3)
Between ENOFR and CLK (Note 3)
Between ENOFR and CLK (Note 3)
After ENOFR, before analog output change
5
-
-
2
-
-
4
-
-
-
14
-
Write Enable Pulse Width, tWR
Write Enable Setup Time, tWS
Write Enable Hold Time, tWH
RESET Pulse Width, tRW
RESET Setup Time, tRS
RESET Latency to Output, tRL
WE (Note 3)
Between WE and WR (Note 3)
Between WE and WR (Note 3)
RESET (Note 3)
Between RESET and CLK
After RESET, before analog output reflects reset values
5
-
-
2
-
-
4
-
-
5
-
-
-
2
-
-
11
-
RESET Latency to Write, tRE
After RESET, before the control registers can be written to
-
1
-
UNITS
MSPS
MSPS
ns
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Clock
Cycles
Clock
Cycles
ns
ns
ns
Clock
Cycles
ns
ns
ns
Clock
Cycles
ns
ns
ns
ns
ns
Clock
Cycles
Clock
Cycles
3-8

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