AD7712AN 데이터 시트보기 (PDF) - Analog Devices
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AD7712AN Datasheet PDF : 28 Pages
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AD7712
SPECIFICATIONS (continued)
Parameter
A, S Versions1
Unit
Conditions/Comments
REFERENCE OUTPUT
Output Voltage
Initial Tolerance
Drift
Output Noise
Line Regulation (AVDD)
Load Regulation
External Current
2.5
V nom
±1
% max
20
ppm/°C typ
30
µV typ
pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth
1
mV/V max
1.5
mV/mA max Maximum Load Current 1 mA
1
mA max
VBIAS INPUT13
Input Voltage Range
VBIAS Rejection
LOGIC INPUTS
Input Current
All Inputs except MCLK IN
VINL, Input Low Voltage
VINH, Input High Voltage
MCLK IN Only
VINL, Input Low Voltage
VINH, Input High Voltage
LOGIC OUTPUTS
VOL, Output Low Voltage
VOH, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance14
AVDD – 0.85 ϫ VREF
or AVDD – 3.5
or AVDD – 2.1
VSS + 0.85 ϫ VREF
or VSS + 3
or VSS + 2.1
65 to 85
± 10
0.8
2.0
0.8
3.5
0.4
4.0
± 10
9
V max
V max
V min
V min
dB typ
µA max
V max
V min
V max
V min
V max
V min
µA max
pF typ
See VBIAS Input Section
Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AVDD/VSS
Whichever Is Smaller: +5 V/0 V Nominal AVDD/VSS
See VBIAS Input Section
Whichever Is Greater: +5 V/–5 V or +10 V/0 V
Nominal AVDD/VSS
Whichever Is Greater: +5 V/0 V Nominal AVDD/VSS
Increasing with Gain
ISINK = 1.6 mA
ISOURCE = 100 µA
TRANSDUCER BURNOUT
Current
4.5
Initial Tolerance
± 10
Drift
0.1
µA nom
% typ
%/°C typ
SYSTEM CALIBRATION
AIN1
Positive Full-Scale Calibration Limit15
Negative Full-Scale Calibration Limit15
Offset Calibration Limit16, 17
Input Span15
AIN2
Positive Full-Scale Calibration Limit15
Negative Full-Scale Calibration Limit15
Offset Calibration Limit17
Input Span15
(1.05 ϫ VREF)/GAIN
–(1.05 ϫ VREF)/GAIN
–(1.05 ϫ VREF)/GAIN
0.8 ϫ VREF/GAIN
(2.1 ϫ VREF)/GAIN
(4.2 ϫ VREF)/GAIN
–(4.2 ϫ VREF)/GAIN
–(4.2 ϫ VREF)/GAIN
3.2 ϫ VREF/GAIN
(8.4 ϫ VREF)/GAIN
V max
V max
V max
V min
V max
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
13The AD7712 is tested with the following VBIAS voltages. With AVDD = 5 V and VSS = 0 V, VBIAS = 2.5 V; with AVDD = 10 V and VSS = 0 V, VBIAS = 5 V and
with AVDD = 5 V and VSS = –5 V, VBIAS = 0 V.
14Guaranteed by design, not production tested.
15After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
16These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AV DD + 30 mV or does not go more negative
than VSS – 30 mV.
17The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
REV. F
–3–
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