IDT723622(2015) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT723622
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

CLKB

CSB

tCLK

tCLKH

tCLKL

LOW

W/RB HIGH

MBB LOW

ENB

tENS2

tENH

COMMERCIAL TEMPERATURE RANGE

ORB HIGH

tA

B0 -B35

CLKA

Previous Word in FIFO1 Output Register

tSKEW1(1)

tCLK

tCLKH

tCLKL

1

Next Word From FIFO1

2

IRA FIFO1 Full

tPIR

tPIR

CSA LOW

W/RA HIGH

MBA

ENA

A0-A35

tENS2

tENH

tENS2

tENH

tDS

tDH

Write

To FIFO1

3022 drw 12

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.

Figure 10. IRA Flag Timing and First Available Write when FIFO1 is Full

18

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