MC14070B 데이터 시트보기 (PDF) - Motorola => Freescale

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MC14070B

Quad Exclusive “OR” and “NOR” Gates

Motorola => Freescale 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic

VDD

Symbol Vdc

– 55_C

Min

Max

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = VDD or 0

“0” Level VOL

5.0

—

0.05

10

—

0.05

15

—

0.05

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = 0 or VDD

“1” Level VOH 5.0 4.95

—

10 9.95

—

15 14.95

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage

“0” Level VIL

(VO = 4.5 or 0.5 Vdc)

5.0

—

1.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 9.0 or 1.0 Vdc)

10

—

3.0

(VO = 13.5 or 1.5 Vdc)

15

—

4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ “1”Level VIH

(VO = 0.5 or 4.5 Vdc)

5.0

3.5

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.0 or 9.0 Vdc)

10

7.0

—

(VO = 1.5 or 13.5 Vdc)

15

11

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Drive Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 2.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.4 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Capacitance

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Vin = 0)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Quiescent Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Per Package)

IOH

Source

Sink IOL

Iin

Cin

IDD

5.0 – 3.0

—

5.0 – 0.64

—

10 – 1.6

—

15 – 4.2

—

5.0 0.64

—

10

1.6

—

15

4.2

—

15

—

± 0.1

—

—

—

5.0

—

0.25

10

—

0.5

15

—

1.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Total Supply Current**†

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Dynamic plus Quiescent,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Per Package)

(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ buffers switching)

IT

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Rise and Fall Times**

tTLH,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (CL = 50 pF)

tTHL

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

5.0

—

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

10

—

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL = (0.40 ns/pF) CL + 20 ns

15

—

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Times**

tPLH,

(CL = 50 pF)

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.90 ns/pF) CL + 130ns

5.0

—

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.36 ns/pF) CL + 57 ns

10

—

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.26 ns/pF) CL + 37 ns

15

—

—

25_C

Min

Typ #

Max

—

0

0.05

—

0

0.05

—

0

0.05

4.95

5.0

—

9.95

10

—

14.95

15

—

—

2.25

1.5

—

4.50

3.0

—

6.75

4.0

3.5

2.75

—

7.0

5.50

—

11

8.25

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

0.51

0.88

1.3

2.25

3.4

8.8

— ± 0.00001

—

5.0

—

—

—

—

—

—

—

± 0.1

7.5

—

0.0005 0.25

—

0.0010

0.5

—

0.0015

1.0

IT = (0.3 µA/kHz) f + IDD

IT = (0.6 µA/kHz) f + IDD

IT = (0.9 µA/kHz) f + IDD

—

100

200

—

50

100

—

40

80

—

175

350

—

75

150

—

55

110

125_C

Min

Max

—

0.05

—

0.05

—

0.05

4.95

—

9.95

—

14.95

—

—

1.5

—

3.0

—

4.0

3.5

—

7.0

—

11

—

– 1.7

– 0.36

– 0.9

– 2.4

0.36

0.9

2.4

—

—

—

—

—

—

—

—

—

± 1.0

—

Unit

Vdc

Vdc

Vdc

Vdc

mAdc

mAdc

µAdc

pF

—

7.5 µAdc

—

15

—

30

µAdc

ns

—

—

—

—

—

—

ns

—

—

—

—

—

—

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

** The formulas given are for the typical characteristics only at 25_C.

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,

precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance

circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must

be left open.

MC14070B MC14077B

2

MOTOROLA CMOS LOGIC DATA

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