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CDP1879

CMOS Real-Time Clock

Intersil 

CDP1879, CDP1879C-1

250ms of the address “1” access. In memory mapping any

dummy write operation after selecting address “1” will set the

“freeze” circuit. If using the I/O mode, a 61 output instruction

will perform the same function. There is no time restriction

on subsequent accesses as long as the read or write opera-

tions are preceded by selecting address “1”.

Power Down

Power down operation is initiated with a low signal on the

"POWER DOWN” input pin. In conjunction with the interrupt

output, it is used to supply external control circuits with a 3

level control signal. The operating current is not appreciably

reduced during “POWER DOWN” operation. When power

down is initiated, any inputs on the address or data bus are

ignored. The clock output is set low. The interrupt output is

three-stated. If enabled previously, the alarm circuitry is

active and will set the interrupt output pin low when alarm

time occurs. The interrupt output will also go low if a clock

was selected and an internal high-to-low transition occurs

during power down. The clock output pin will remain low. If

power down is initiated in the middle of a read or write

sequence, it will not become activated until the read or write

cycle is completed.

Microprocessor Real-Time Clock

MRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RD

TPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPB/WR

TPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPA

N LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADDRESS LINES

IO/MEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD

CS - CHIP SELECT - Used to enable or disable the inputs

and outputs. TPA is used to strobe and latch a positive level

on this pin to enable the device.

XTAL AND XTAL - The frequency of the internal oscillator is

determined by the value of the crystal connected to these

pins. “XTAL” may be driven directly by an external frequency

source.

Clock Out - 1 of 15 square wave frequencies will appear at

this pin when selected. During power down, this pin will be

placed low, and will be high during normal operation when

the clock is deselected.

Power Down - Power Down Control - A low on this pin will

place the device in the power down mode.

Pin Functions

VDD, VSS - Power and ground for device.

DB0 - DB7 - DATA BUS - 8-bit bidirectional bus that trans-

fers BCD data to and from the counters, latches and regis-

ters.

INT - Interrupt Output - A low on this pin indicates an active

alarm time or high-to-low transition of the “clock out” signal.

RESET - A low on this pin clears the status register and

places the interrupt output pin high.

Frequency Input Requirements

A0, A1, A2 - Address inputs that select a counter, latch or

register to read from or write to.

TPA - Strobe input used to latch the value on the chip select

pin. CS is latched on the trailing edge of TPA. During mem-

ory mapping, it is used to latch the high order address bit

used for the chip select. When the real-time clock is used

with other microprocessors, or when the high order address

of the CDP1800 series microprocessor is externally latched,

it is connected to VDD. In the input/output mode, it is used to

gate the N lines.

IO/MEM - Tied low during memory mapping and high when

the input/output mode of the CDP1800 series microproces-

sor is used.

The Real-Time Clock operates with the following frequency

input sources:

1. An external crystal that is used with the on-board oscilla-

tor. The oscillator is biased by a large feedback resistor

and oscillates at the crystal frequency (see Figure 6,

Table 3).

2. An external frequency input that is supplied at the XTAL

input. XTAL is left open (see Figure 5). A typical external

oscillator circuit is shown in Figure 7 in section, “Standby

(Timekeeping) Voltage Operation”.

RD, TPB/WR - Direction Signals - Active signals that deter-

mine data direction flow. In the memory mapped mode, data

is placed on the bus from the counters or status register

when RD pin is active.

Data is transferred to a counter, latch or the control register

when RD is high and TPB/WR is active and latched on the

trailing edge (low to high) of the TPB/WR signal.

In the input/output mode, data is placed on the bus from a

counter or status register when RD is not active between the

trailing edges of TPA and TPB. Data on the bus is written to a

counter, latch, or the control register during TPB when RD is

active and latched on TPB's trailing edge. The following con-

nections are required between the microprocessor and real-

time clock in the CDP1800 series I/O mode.

4-114

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