LH5164A 데이터 시트보기 (PDF) - Sharp Electronics

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LH5164A

CMOS 64K (8K × 8) Static RAM

Sharp Electronics 

CMOS 64K (8K × 8) Static RAM

LH5164A/AH

tWC

A0 - A12

OE

CE1

CE2

WE

DOUT

DIN

tAW

tCW

(NOTE 2)

(NOTE 4)

tWR

tCW

tWR

tAS

(NOTE 3)

(NOTE 5)

tOHZ

(NOTE 6)

tWP

tWR

(NOTE 1)

HIGH-Z

tDW

tDH

DATA VALID

NOTES:

1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,

to the time when the writing is finished.

3. tAS is defined as the time from address change to writing start.

4. tWR is defined as the time from writing finish to address change.

5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the

outputs will remain high-impedance.

6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.

Figure 6. Write Cycle 1

5164A-4

7

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