CDP1826CE 데이터 시트보기 (PDF) - Intersil

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CDP1826CE

CMOS 64-Word x 8-Bit Static RAM

Intersil 

A0 - A5

TPA

MWR

CS1 • CS2

BUS

CDP1826C

HIGH ORDER

ADDRESS BYTE

tASH

tAH

LOW ORDER ADDRESS BYTE

tASL

tWR

tPAW

tWW

tCS

VALID CHIP SELECT

tDS

DATA IN STABLE

tDH1, tDH2

FIGURE 6. TIMING WAVEFORMS FOR WRITE-CYCLE 1

A0 - A5

MWR

CS1 • CS2

BUS

HIGH ORDER

ADDRESS BYTE

LOW ORDER ADDRESS BYTE

tASL

tWR

tWW

tCS

VALID CHIP SELECT

tDS

DATA IN STABLE

tDH1, tDH2

FIGURE 7. TIMING WAVEFORMS FOR WRITE-CYCLE 2 (TPA = HIGH)

6-54

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