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CDP1882

CMOS 6-Bit Latch and Decoder Memory Interfaces

Intersil 

CDP1881C, CDP1882, CDP1882C

Static Electrical Specifications At TA = -40oC to +85oC, VDD ± 5%, Except as Noted: (Continued)

CONDITIONS

CDP1882

CDP1881C, CDP1882C

PARAMETER

VO

SYMBOL (V)

VIN

VDD

(NOTE 1)

(NOTE 1)

(V)

(V)

MIN

TYP

MAX MIN

TYP

MAX UNITS

Input Leakage Current

IIN

Any

0, 5

5

-

Input

0, 10

10

-

-

±1

-

-

±2

-

-

±1

µA

-

-

µA

Operating Current

(Note 2)

IDD1

0, 5

0, 5

5

-

-

2

-

-

2

mA

0, 10 0, 10

10

-

-

4

-

-

-

mA

Input Capacitance

Output Capacitance

Minimum Data

Retention Voltage

CIN

COUT

VDR

-

-

-

-

-

-

VDD = VDR

-

5

7.5

-

-

10

15

-

-

2

2.4

-

5

7.5

pF

10

15

pF

2

2.4

V

Data Retention Current

IDR

VDD = 2.4V

-

0.01

1

-

0.5

5

µA

NOTES:

1. Typical values are for TA = +25oC.

2. IOL = IOH = 1µA.

3. Operating current measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with outputs open circuits (equivalent to typical CDP1800

system at 3.2MHz, 5V; and 6.4MHz, 10V).

MA0 7

MA1 6

MA2 5

MA3 4

MA4 3

MA5 2

CLOCK 1

MRD 8

MWR 9

CE 11

DQ

C

DQ

C

DQ

C

DQ

C

DQ

CQ

DQ

CQ

19 A8

18 A9

17 A10

16 A11

MA0 7

MA1 6

MA2 5

MA3 4

15 CS0

MA4 3

14 CS1

13 CS2

12 CS3

MA5 2

CLOCK 1

VDD = 20

VSS = 10

CE 8

DQ

C

DQ

C

DQ

C

DQ

C

DQ

CQ

DQ

CQ

17 A8

16 A9

15 A10

14 A11

13 CS0

12 CS1

11 CS2

10 CS3

VDD = 18

VSS = 9

FIGURE 1. FUNCTIONAL DIAGRAM FOR THE CDP1881C

FIGURE 2. FUNCTIONAL DIAGRAM FOR THE CDP1882,

CDP1882C

4-3

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