LH52256CN-70LL 데이터 시트보기 (PDF) - Sharp Electronics

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LH52256CN-70LL

CMOS 256K (32K × 8) Static RAM

Sharp Electronics 

LH52256C/CH

CMOS 256K (32K × 8) Static RAM

ADDRESS

CE

WE

DOUT

DIN

tWC

tAW

tCW

(NOTE 2)

tAS

(NOTE 3)

tWP

(NOTE 1)

tWR (NOTE 4)

tWR

(NOTE 4)

(NOTE 6)

tWZ

(NOTE 5)

tOW

(NOTE 7)

tDW

tDH

DATA VALID

NOTES:

1. A write occurs during the overlap of a LOW CE, and a LOW WE.

A write begins at the latest transition among CE going LOW, and

WE going LOW. A write ends at the earliest transition among CE

going HIGH, and WE going HIGH. tWP is measured from the beginning

of write to the end of write.

2. tCW is measured from the later of CE going LOW to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change.

5. During this period, I/O pins are in the output state, therefore the input

signals of opposite phase to the outputs must not be applied.

6. If CE goes LOW simultaneously with WE going LOW or after WE going

LOW, the outputs remain in high impedance state.

7. If CE goes HIGH simulaneously with WE going HIGH or before WE

going HIGH, the outputs remain in high impedance state.

Figure 6. Write Cycle (OE Low Fixed)

52256C-5

CE CONTROL

VCC

4.5 V

2.2 V

VCCDR

CE

0V

DATA RETENTION MODE

tCDR

tR

CE ≥ VCCDR - 0.2 V

Data Retention Timing Chart

CE Controlled

52256C-6

8

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