TDF8599B 데이터 시트보기 (PDF) - NXP Semiconductors.
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TDF8599B Datasheet PDF : 54 Pages
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NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect
of the external oscillator signal connected to pin OSCIO. Phase lock operation is also
needed to enable phase staggering, see Section 8.4.2 on page 13. Phase lock operation
is enabled when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and
CPLL_p) and a resistor (RPLL) between pin SSM and pin AGND (see Figure 8). Connecting
pin SSM to pin AGND disables phase lock operation and causes the slave to directly use
the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on the desired
loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BPLL Ω. The
corresponding values for CPLL_s and CPLL_p are given by Equation 3 and Equation 4:
CPLL_p = -R---P----L-0-L--.--0×---3--B-2---P---L---L- [F ]
(3)
Remark: CPLL_p is only needed when 1⁄4 π phase shift is selected. See Section 8.4.2 for
more detailed information.
CPLL_s = -R---P----L--L--0--×-.--8--B----P---L---L- [F ]
(4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BPLL should be 100 × fSSM.
100 µA
OSCSET
100 µA
OSCSET
SSM
PLL
PLL
SSM
CPLL_s
RPLL
CPLL_p(1)
001aai776
a. Off
Fig 8. Phase lock operation
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(1) Only needed when 1⁄4 π phase shift is
selected.
b. On
Table 7 lists all oscillator modes.
Table 7. Oscillator modes
OSCSET pin OSCIO pin
Rosc > 26 kΩ
Rosc > 26 kΩ
Rosc = 0 Ω
Rosc = 0 Ω
output
output
input
input
SSM pin
CSSM to pin AGND
shorted to pin AGND
CPLL + RPLL to pin AGND
shorted to pin AGND
Oscillator modes
master, spread spectrum
master, no spread spectrum
slave, PLL enabled
slave, PLL disabled
TDF8599B_1
Product data sheet
Rev. 01 — 29 July 2009
© NXP B.V. 2009. All rights reserved.
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