TDA9112A 데이터 시트보기 (PDF) - STMicroelectronics
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TDA9112A Datasheet PDF : 60 Pages
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TDA9112A
Table 1. Horizontal section ( Vcc = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Picture geometry corrections through PLL1 & PLL2
tHph /TH
Hor. VCO phase vs. sync signal (via
PLL1), see Figure 7
HPOS (Sad01h):
11111111b
10000000b
00000000b
tPCAC /TH
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
PCAC (Sad11h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
tParalC /TH
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
PARAL (Sad12h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
tTCAC /TH
Contribution of top corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
TCAC (Sad13h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
tBCAC /TH
BCAC (Sad14h) full span
(9)
Contribution of bottom corner asymmetry
correction to phase of H-drive vs. static VPOS at medium
phase (via PLL2), measured in corners VSIZE at minimum
VSIZE at medium
VSIZE at maximum
Min.
Value
Typ.
+11
0
-11
±0.9
±1.6
±2.6
±1.4
±1.9
±2.4
±0.4
±1.4
±3.5
±0.4
±1.4
±3.5
Max.
Units
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
Notes about horizontal section
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate
the free-running frequency is fHO(0)=0.122/(RRO CCO)
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500Ω and a resistance to ground of about 20kΩ.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 6.
Note 7: The tph(min) parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
11/60
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