TDA9910 데이터 시트보기 (PDF) - Philips Electronics
부품명
상세내역
일치하는 목록
TDA9910
Philips Electronics
TDA9910 Datasheet PDF : 21 Pages
| |||
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
Table 5: Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C
to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at
VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Test [1] Min
Typ
Max
Unit
SFDR spurious free dynamic
range TDA9910/6
fi = 21.4 MHz
fi = 93 MHz
-
76
-
dBc
-
73
-
dBc
spurious free dynamic
range TDA9910/8
fi = 175 MHz
fi = 21.4 MHz
fi = 93 MHz
-
73
-
dBc
-
79
-
dBc
-
75
-
dBc
fi = 175 MHz
-
72
-
dBc
ACPR adjacent channel power fi = 93 MHz; 5 MHz
-
86
-
dB
rejection
channel spacing;
B = 4.096 MHz
fi = 175 MHz; 5 MHz
-
74
-
dB
channel spacing;
B = 4.096 MHz
d2(IM2)
second order
intermodulation
distortion [8]
d3(IM3)
third order
intermodulation
distortion [8]
fi1 = 21 MHz;
fi2 = 22 MHz
fi1 = 93 MHz;
fi2 = 96 MHz
fi1 = 174 MHz;
fi2 = 176 MHz
fi1 = 21 MHz;
fi2 = 22 MHz
fi1 = 93 MHz;
fi2 = 96 MHz
fi1 = 174 MHz;
fi2 = 176 MHz
-
−81
-
-
−83
-
-
−80
-
-
−87
-
-
−88
-
-
−83
-
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
[1] D = guaranteed by design;
C = guaranteed by characterization;
I = 100 % industrially tested.
[2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLKN or CLK input to DGND via a 100 nF capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case CLKN pin has to be connected to the ground.
[3] The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to VCCA.
[4] Output data acquisition: the output data is available after the maximum delay of td(o).
[5] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[6] The total harmonic distortion is obtained with the addition of the first five harmonics.
[7] The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
9397 750 14418
Objective data sheet
Rev. 02 — 9 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9 of 21
Share Link: