7025E 데이터 시트보기 (PDF) - MAXWELL TECHNOLOGIES

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7025E

(8K x 16-Bit) Dual Port RAM High-Speed CMOS

MAXWELL TECHNOLOGIES 

(8K x 16-Bit) Dual Port RAM High-Speed CMOS

7025E

FIGURE 1. TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE1,2,3

FIGURE 2. TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE1,4,5

1. F/W is high for read cycles.

2. Device is continuously enabled, CS = VIL, UB or LB = VL. This waveform cannot be used for semaphore reads.

3. CE = VIL.

4. Addresses valid prior to or coincident with CS transition.

5. To access RAM, CS = VL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL.

1000586

12.19.01 Rev 2

All data sheets are subject to change without notice 10

©2001 Maxwell Technologies

All rights reserved.

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