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TC581282A Datasheet PDF : 31 Pages
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TC581282AXB
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
512
16
I/O1
I/O8
A page consists of 528 bytes in which 512 bytes are used
for main memory storage and 16 bytes are for redundancy
or for other uses.
32768 pages
1024 blocks
32 pages
1 block
1 page = 528 bytes
1 block = 528 bytes × 32 pages = (16K + 512) bytes
Capacity = 528 bytes × 32 pages × 1024 blocks
An address is read in via the I/O port over three
consecutive clock cycles, as shown in Table 1.
8I/O
528
Figure 2. Schematic Cell Layout
Table 1. Addressing
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
First cycle
A7 A6 A5 A4 A3 A2 A1 A0
Second cycle
A16 A15 A14 A13 A12 A11 A10 A9
Third cycle
*L A23 A22 A21 A20 A19 A18 A17
*: A8 is automatically set to Low or High by a 00H command or a 01H command.
*: I/O8 must be set to Low in the third cycle.
A0~A7: Column address
A9~A23: Page address
A14~A23: Block address
A9~A13: NAND address in block
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command
operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE,
ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic table
CLE
ALE
CE
WE
RE
WP *1
Command Input
H
L
L
H
*
Address Input
L
H
L
H
*
Data Input
L
L
L
H
H
Serial Data Output
L
L
L
H
*
During Read (Busy)
*
*
L
H
H
*
*
*
H
*
*
*
During Programming (Busy)
*
*
*
*
*
H
During Erasing (Busy)
*
*
*
*
*
H
Program, Erase Inhibit
Standby *2
*
*
*
*
*
L
*
*
H
*
*
0 V/Vcc
H: VIH, L: VIL, *: VIH or VIL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: The device does not go into a low-power Standby mode when CE goes High during Busy state of a Read, Program or Erase
operation.
2001-12-04 14/31
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