RF2456 데이터 시트보기 (PDF) - RF Micro Devices
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RF2456 Datasheet PDF : 8 Pages
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RF2456
Pin Function Description
Interface Schematic
1
VCC
Supply Voltage for the mixers, bias circuits, and control logic. External
RF and IF bypassing is required. The trace length between the pin and
VCC2
the bypass capacitors should be minimized. The ground side of the
BIAS
bypass capacitors should connect immediately to ground plane.
LO OUT
2
IF2-
Same as pin 3, except complimentary output. For typical single ended See pin 3.
operation, this pin is connected directly to VCC.
3
IF2+
FM IF Output pin. This is a balanced output, but is typically used as a
single-ended output. The internal circuitry, in conjunction with an exter-
nal matching/bias inductor to VCC, sets the operating impedance. This
inductor is typically incorporated in the matching network between the
output and IF filter. The net output impedance, including the external
inductor, is about 870Ω at 85MHz. Because this pin is biased to VCC, a
DC blocking capacitor must be used if the IF filter input has a DC path
to ground. See Application Schematic.
IF2+ IF2-
8.5 pF
2.1 kΩ
4
GND
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
6
5
IF 1+
CDMA IF Output pin. This is a balanced output. The internal circuitry, in
conjunction with an external matching/bias inductor to VCC, sets the
operating impedance. This inductor is typically incorporated in the
matching network between the output and IF filter. The net output
impedance, including the external inductor, at 85MHz is higher than
1kΩ, even though the part is designed to drive a 1kΩ load. Because
this pin is biased to VCC, a DC blocking capacitor must be used if the IF
filter input has a DC path to ground. See Application Schematic.
IF1+ GND2 IF1-
1.2 1.2
pF pF
6
IF 1-
Same as pin 5, except complementary output.
See pin 5.
7
IF SELECT Control line for IF out select. A logic “low” enables the FM output. A
logic “high” enables the CDMA output. The threshold voltage is 1.6V,
and the pin draws less than 50µA when selected.
50 kΩ
C1
8
PD
Power down pin. A logic “low” turns the part off. A logic “high” (>1.6V)
turns the part on. In addition, pin 7 (IF SELECT) should also be taken
50 kΩ
PD
low during power down.
9
LO IN+
Mixer LO Balanced Input Pin. For single-ended input operation, this pin
LO IN+
LO IN-
is used as an input and pin 10 is bypassed to ground.
10
LO IN-
Same as pin 9 except complementary input.
See pin 9.
11
GND
Ground connection for the mixer. For best performance, keep traces
physically short and connect immediately to ground plane.
12
MIX IN
Mixer RF Input Pin. This pin is internally DC biased and should be DC
blocked if connected to a device with DC present. External matching
network sets RF and IF impedance for optimum performance.
MIX IN
13
BYP
Internal voltage reference. External RF and IF bypassing is required.
The trace length between the pin and the bypass capacitors should be
minimized. The ground side of the bypass capacitors should connect
immediately to ground plane.
14
GND
Same as pin 4.
15
GND
Same as pin 4.
16
GND
Same as pin 4.
Rev B6 010717
6-3
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