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HFA3665IA

CDMA/AMPS Downconverter with AGC Capability

Intersil 

HFA3665

DESIGN INFORMATION

External AGC Application Components Description

(Please refer to Typical RF and Front End AGC Application Diagram)

NOTE:In order to avoid input insertion losses and maintain the Noise

Figure of this application optimized, the VSWR of the LNA input at-

tenuator scheme is directly impacted by the input shunt PIN diode im-

pedance when AGC is in action. This mismatch is absorbed by the

duplexer/filter and there is no significant impact in its duplex charac-

teristics to both antenna and transmitter ports.

R3 and R4 limit the output attenuation range and output

VSWR.

R1 sets the scale factor, temperature coefficient and range

of the gain control voltage.

R2 sets the turn-on point for the output PIN diode attenuator

and R5 sets the turn-on point for the input PIN diode attenu-

ator by shunting to ground some of the PIN diode bias cur-

rent. By making R5 a smaller value than R2, the output

attenuator turns on first, to optimize NF. Making R5 = R2 will

turn both PIN diodes simultaneously to optimize the IIP3 dur-

ing the initial AGC action. The R2/R5 combination can be tai-

lored to specific AGC characteristics.

R6 generates the reference current which is used to set the

operating point of all the major RF and IF transistors. A pro-

portional to temperature (PTAT) voltage of about

37mVat25oC is applied to this resistor. PTAT biasing keeps

the gain temperature independent. A 10% variation from

523Ω is allowed. Lower values increase the total LNA and

Mixer bias currents.

C1 filters noise from the gain control source to reduce

unwanted AM modulation.

LE adds degeneration to the LNA input for higher input inter-

cept points. This combination of degeneration and a higher

LNA VCC (VLNA) improves considerably the input intercept

point with a slight decrease in gain. LE shall have very high

Q and can be build with a small PC trace.

L1 and L4 permit DC biasing of the PIN diodes and RF iso-

lation. Several types of 82nH inductors have SRF near

900MHz thus maximizing the RF isolation.

L2 and C13 are part of the output matching network and

provides the DC bias path for the open collector output.

R7 and R8 define the Real part of the CDMA and FM output

ports impedances. Unloaded “Q” of the coils used for proper

biasing of these ports have to be taken into account when

defining these values. The total load presented to these

ports also define the achievable gain of the mixers. Because

there is no internal feedback between the complementary

ports of the differential channel, the loads and ports can be

split into independent ports referenced to ground.

L7, L8 and L9, L10 have two functions: They provide a DC

path to ground required for proper operation of the CDMA

and FM differential outputs and can also be part of the match

network between these ports and IF filters. C9, C10 and C12

are part of a match network to the suggested filters. L9, L10

and C12 are part of a current summer network for a differen-

tial to single end conversion. L12, L13 and C11 form a high

“Q” match network between the converter and the sug-

gested filter for the SAW IP3 distortion optimization.

C2 and C4 provide DC isolation for PIN diode biasing. Their All other unlabeled components on the schematics are

values are chosen to provide series resonance cancelling of bypass/decoupling capacitors. Values are chosen based on

the diode package and PC board inductances.

their SRF.

C3 and C6 decouple the PIN diode bias pins. Failure to

decouple these pins may cause LNA oscillations.

7

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