CDP1852E 데이터 시트보기 (PDF) - Intersil
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CDP1852E Datasheet PDF : 9 Pages
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CDP1852, CDP1852C
CS1 ⋅ CS2
(NOTE 1)
CLOCK
tWW (NOTE 2)
tSH
tDH
tDS
tCLK
DATA IN
DATA OUT
tRDO
tDDO
SR
tRSR
tCLR
tWDO
tSSR
tCSR
CLEAR
NOTES
1. CS1 • CS2 is the overlap of CS1 = 0 and CS2 = 1.
2. Write is the overlap of CS1 • CS2 and CLOCK.
MODE 1 TRUTH TABLE
SERVICE REQUEST TRUTH TABLE
CLOCK † CS1-CS2 CLEAR
0
X
0
0
X
1
X
0
1
1
1
X
† CS1 • CS2 : CS1 = 0, CS2 = 1
DATA OUT EQUALS
0
Data Latch
Data Latch
Data In
CS1
or
CS2
SR/SR 1
CLOCK
or
CLEAR
SR/SR 0
FIGURE 6. MODE 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
MEMORY
ADDRESS
LINES
CDP1802
NX
MRD
TPB
VDD
CDP1852
CS2
CS1
CLOCK
DATA
OUT
SR
MODE DATA IN
DATA OUT TO
PERIPHERAL DEVICE
SIGNAL THAT INDICATES
DATA IS READY
DATA BUS
NX
TPB
MRD
CDP1852 IS SELECTED
AND DATA IS
STROBED INTO IT’S
REGISTER WITH TPB
DATA BUS
VALID
DATA
DATA TO
PERIPHERAL
DEVICE
SR/SR
DATA IS OUTPUTTED
FROM THE CDP1852
AND THE PERIPHERAL
DEVICE IS SIGNALED
FIGURE 7. OUTPUT PORT MODE 1 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
8
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