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HSP50307SC Datasheet PDF : 9 Pages
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HSP50307
Control Interface
Synthesizer
The QPSK modulator is configured via a serial three wire
interface. When C_EN is high, 23 bits are shifted in at the
CDATA pin on the falling edge of CCLK. Figure 3 shows the
timing diagram for loading the serial configuration data.
Table 1 describes the 23-bit serial configuration data. See
the Synthesizer Section for more details on the frequency
control bits.
TABLE 1. 23-BIT SERIAL DATA CONTROL INTERFACE
DESCRIPTION
BIT
POSITION FUNCTION
DESCRIPTION
D0-D2
(Note)
Synthesizer Pre-scaler control register.
Control Bits A = (0 to 5), D2 is the MSB.
D3-D9
Synthesizer Feedback Counter Control Register.
Control Bits M = (41 to 103) D9 is the MSB.
D10
Synthesizer Active high. This bit activates chip bias
Enable
networks for normal operation. D10 = 0
places part in low power mode.
D11
Charge Pump D11 = 0 sets charge pump current to
Current
500µA.
Control
D11 = 1 sets charge pump current to
1mA.
D12
Three-State D12 = 0 three-states the charge pump
Control
output when a pump up and down
command occur simultaneously.
D12 = 1 disables three-state.
D13-D18
Attenuation
Control
Controls output power level. The bi-
nary value of the register corresponds
to an attenuation amount. For exam-
ple, 000100 corresponds to 4dB at-
tenuation from the maximum 62dBmV
level.
D18 is the MSB.
D19-D21 Reserved
Used for test/diagnostic purposes.
Set to 000.
D22
DSP Shut Test mode; D22 = 0 sets the burst
Down
QPSK modulator in normal mode.
D22 = 1 disables the digital filter.
The synthesizer generates the quadrature LO’s for
modulating the baseband data to RF. The carrier frequency
is phase locked to the reference clock (RCLK). The carrier
frequency, FC, has a frequency range of 8MHz to 15MHz
with a resolution of 32kHz. Equation 1 gives the relationship
between FC and the frequency of RCLK and the frequency
control bits, M and A.
FC
=
6----(---M------+-----1----)---+-----A---
64
FREF
,
(EQ. 1)
where FREF equals the frequency of RCLK. Also, M and A
can be determined by
M
+
A---
6
=
6----4--
6
----F----C------
FREF
– 1.
(EQ. 2)
“A” ranges from 0 to 5 and “M” ranges from 41 to 103. A and
M are programmed via control bits D0-D2 and D3-D9,
respectively. Values outside these ranges are invalid.
I/Q Generator
The I/Q Generator Section demultiplexes and time aligns the
256 KBPS input data into two data streams, I and Q. The
first data bit following the assertion of the TX_EN signal is
the I data of the first I/Q pair. Each I/Q pair determines the
phase angle of the QPSK transmission signal. The relation-
ship between I/Q pairs and phase angles is shown in
Table 2. Since the QPSK encoding requires a pair of I and Q
information to transmit one symbol, an even number of data
bits must be provided for each burst.
TABLE 2. QPSK ENCODING
I
Q
PHASE
0
0
45o
0
1
135o
1
0
-45o
1
1
-135o
NOTE: D0 is the first bit shifted into the part.
4
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