STM708ADS6E 데이터 시트보기 (PDF) - STMicroelectronics

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STM708ADS6E

5 V supervisor

STMicroelectronics 

Pin descriptions

2

Pin descriptions

STM705, STM706, STM707, STM708, STM813L

2.1

MR

A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low

and for trec after MR returns high. This active-low input has an internal pull-up. It can be

driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if

unused.

2.2

WDI

If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset

(or WDO) is triggered. The internal watchdog timer clears while reset is asserted or when

WDI sees a rising or falling edge.

The watchdog function can be disabled by allowing the WDI pin to float.

2.3

Note:

WDO

It goes low when a transition does not occur on WDI within 1.6 s, and remains low until

a transition occurs on WDI (indicating the watchdog interrupt has been serviced). WDO also

goes low when VCC falls below the reset threshold; however, unlike the reset output, WDO

goes high as soon as VCC exceeds the reset threshold. Output type is push-pull.

For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO

is connected to MR.

2.4

RST

Pulses low when triggered, and stays low whenever VCC is below the reset threshold or

when MR is a logic low. It remains low for trec after either VCC rises above the reset

threshold, or MR goes from low to high.

2.5

RST

Goes high with triggered, and stays high whenever VCC is above the reset threshold or

when MR is a logic high. It stays high for trec after either VCC falls below the reset threshold,

or MR goes from high to low.

2.6

PFI

When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Connect to

ground if unused.

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Doc ID 10520 Rev 9

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