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STM795RDS6F

3V Supervisor with Battery Switchover

STMicroelectronics 

STM690/704/795/802/804/805/806

OPERATION

Reset Output

The STM690/704/795/802/804/805/806 Supervi-

sor asserts a reset signal to the MCU whenever

VCC goes below the reset threshold (VRST), a

watchdog time-out occurs, or when the Push-but-

ton Reset Input (MR) is taken low. RST is guaran-

teed to be a logic low (logic high for STM804/805)

for 0V < VCC < VRST if VBAT is greater than 1V.

Without a back-up battery, RST is guaranteed val-

id down to VCC =1V.

During power-up, once VCC exceeds the reset

threshold an internal timer keeps RST low for the

reset time-out period, trec. After this interval RST

returns high.

If VCC drops below the reset threshold, RST goes

low. Each time RST is asserted, it stays low for at

least the reset time-out period (trec). Any time VCC

goes below the reset threshold the internal timer

clears. The reset timer starts when VCC returns

above the reset threshold.

Push-button Reset Input (STM704/806)

A logic low on MR asserts reset. Reset remains

asserted while MR is low, and for trec (see Figure

37., page 24) after it returns high. The MR input

has an internal 40kΩ pull-up resistor, allowing it to

be left open if not used. This input can be driven

with TTL/CMOS-logic levels or with open-drain/

collector outputs. Connect a normally open mo-

mentary switch from MR to GND to create a man-

ual reset function; external debounce circuitry is

not required. If MR is driven from long cables or

the device is used in a noisy environment, connect

a 0.1µF capacitor from MR to GND to provide ad-

ditional noise immunity. MR may float, or be tied to

VCC when not used.

Watchdog Input (NOT available on STM704/

795/806)

The watchdog timer can be used to detect an out-

of-control MCU. If the MCU does not toggle the

Watchdog Input (WDI) within tWD (1.6sec typ), the

reset is asserted. The internal watchdog timer is

cleared by either:

1. a reset pulse, or

2. by toggling WDI (high-to-low or low-to-high),

which can detect pulses as short as 50ns. If

WDI is tied high or low, a reset pulse is

triggered every 1.8sec (tWD + trec).

The timer remains cleared and does not count for

as long as reset is asserted. As soon as reset is re-

leased, the timer starts counting (see Figure

38., page 24).

Note: Input frequency greater than 20ns (50MHz)

will be filtered.

Back-up Battery Switchover

In the event of a power failure, it may be necessary

to preserve the contents of external SRAM

through VOUT. With a backup battery installed with

voltage VBAT, the devices automatically switch the

SRAM to the back-up supply when VCC falls.

Note: If back-up battery is not used, connect both

VBAT and VOUT to VCC.

This family of Supervisors does not always con-

nect VBAT to VOUT when VBAT is greater than VCC.

VBAT connects to VOUT (through a 100Ω switch)

when VCC is below VSW (2.4V) or VBAT (whichever

is lower). This is done to allow the back-up battery

(e.g., a 3.6V lithium cell) to have a higher voltage

than VCC.

Assuming that VBAT > 2.0V, switchover at VSO en-

sures that battery back-up mode is entered before

VOUT gets too close to the 2.0V minimum required

to reliably retain data in most external SRAMs.

When VCC recovers, hysteresis is used to avoid

oscillation around the VSO point. VOUT is connect-

ed to VCC through a 3Ω PMOS power switch.

Note: The back-up battery may be removed while

VCC is valid, assuming VBAT is adequately decou-

pled (0.1µF typ), without danger of triggering a re-

set.

Table 4. I/O Status in Battery Back-up

Pin

Status

VOUT Connected to VBAT through internal switch

VCC Disconnected from VOUT

PFI Disabled

PFO Logic Low

E High impedance

ECON Logic High

WDI Watchdog timer is disabled

MR Disabled

RST Logic Low

RST Logic High

VBAT Connected to VOUT

Vccsw Logic High (STM795)

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