STK12C68 데이터 시트보기 (PDF) - Cypress Semiconductor
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STK12C68 Datasheet PDF : 24 Pages
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STK12C68
SRAM Write Cycle
Parameter
Cypress
Parameter
Alt
Description
25 ns
Min Max
35 ns
Min Max
tWC
tAVAV
Write Cycle Time
25
35
tPWE
tWLWH, tWLEH
Write Pulse Width
20
25
tSCE
tELWH, tELEH
Chip Enable To End of Write
20
25
tSD
tDVWH, tDVEH
Data Setup to End of Write
10
12
tHD
tWHDX, tEHDX
Data Hold After End of Write
0
0
tAW
tAVWH, tAVEH
Address Setup to End of Write
20
25
tSA
tAVWL, tAVEL
Address Setup to Start of Write
0
0
tHA
tWHAX, tEHAX
Address Hold After End of Write
0
0
tHZWE [9,10]
ly. tLZWE [9]
tWLQZ
tWHQX
s on Switching Waveforms
program ADDRESS
igns. duction CE
ew Deosing pro WE
Write Enable to Output Disable
Output Active After End of Write
10
13
5
5
Figure 9. SRAM Write Cycle 1: WE Controlled [11, 12]
tWC
tSCE
tHA
tAW
tSA
tPWE
ded foprpNort ong DATA IN
NoItnRpercoodmucmtieonn to su DATA OUT
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
Figure 10. SRAM Write Cycle 2: CE Controlled [11, 12]
tWC
ADDRESS
45 ns
Unit
Min Max
45
ns
30
ns
30
ns
15
ns
0
ns
30
ns
0
ns
0
ns
14 ns
5
ns
tSA
tSCE
tHA
CE
WE
DATA IN
tAW
tPWE
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Document Number: 001-51027 Rev. *C
Page 12 of 24
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