4 BLOCK DIAGRAM
ICONS
ROW0
~ ROW67
SEG0 ~ SEG131
MSTAT
M
/DOF
M/ S
CL
CLS
C0
C1
TEST0
TEST22
HV Buffer Cell Level Shifter
Display
Timing
Generator
Display Data Latch
Oscillator
GDDRAM
132 x 68 bits
Level
Selector
LCD Driving
Voltage
Generator
2X/3X/4X/5X
Regulated
DC/DC
Converter,
Contrast
Control, Bias
Divider,
Temperature
Compensation
Command Decoder
Command Interface
Parallel/Serial Interface
VF
VCI
IRS
VOUT
B0
B1
VLREF
VHREF
VFS
VDD
VDDIO
VSS
VSS1
RES P/ S CS 1 CS2 D/ C E( RD ) C68/( 80 ) R/W ( WR ) D7 D6 D5 D4 D3 D2 D1 D0
(SDA) (SCK)
Figure 1 - SSD1805 Block Diagram
Solomon Systech
Jun 2004 P 6/52 Rev 1.1 SSD1805 Series