SSD1805TR1 데이터 시트보기 (PDF) - Solomon Systech

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SSD1805TR1

132 x 68 STN LCD Segment / Common Monochrome Driver with Controller

Solomon Systech  

6 PIN DESCRIPTION

6.1 MSTAT

This pin is the static indicator driving output. The frame signal output pin, M, should be used as the back

plane signal for the static indicator. The duration of overlapping could be programmable. See Extended

Command Table for details.

6.2 M

This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices while

in slave mode, the pin receives frame signal from the master device.

6.3 CL

This pin is the display clock input/output. In master mode with internal oscillator enabled (CLS pin pulled

high), this pin supplies display clock signal to slave devices. In slave mode or when internal oscillator is

disabled, the pin receives display clock signal from the master device or external clock source.

6.4 /DOF

This pin is display blanking control between master and slave devices. In master mode, this pin supplies

on/off signal to slave devices. In slave mode, this pin receives on/off signal from the master device.

6.5 CS 1, CS2

These pins are the chip select inputs. The chip is enabled for MCU communication only when both CS 1 is

pulled low and CS2 is pulled high.

6.6 RES

This pin is the reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse

width for reset sequence is 20us.

6.7 D/ C

This pin is Data/Command control pin. When the pin is pulled high, the data at D7 - D0 is treated as display

data. When the pin is pulled low, the data at D7 - D0 will be transferred to the command register.

6.8 R/W ( WR )

This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as Read/Write

(R/W ) selection input. Read mode will be carried out when this pin is pulled high and write mode when low.

When 8080 interface mode is selected, this pin is the Write ( WR ) control signal input. Data write operation is

initiated when this pin is pulled low and the chip is selected. When serial interface mode is selected, this pin

must be pulled low.

6.9 E( RD )

This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E)

signal. Read/write operation is initiated when this pin is pulled high and the chip is selected. When 8080

interface mode is selected, this pin is the Read ( RD ) control signal input. Data read operation is initiated

when this pin is pulled low and the chip is selected. When serial interface mode is selected, this pin must be

pulled high.

6.10 D7 - D0

These pins are the 8-bit bi-directional data bus in parallel interface mode. D7 is the MSB while D0 is the LSB.

When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK).

SSD1805 Series Rev 1.1 P 11/52 Jun 2004

Solomon Systech

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