HSP45256 데이터 시트보기 (PDF) - Intersil

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HSP45256

Binary Correlator

Intersil 

HSP45256

Block Diagram

A(2:0)

CLOAD

DECODE

DCONT(7:0)

RLOAD

TXFR

CONFIG

OFFAL

OFFAM

DELAY

OFFBL

OFFBM

MASK

DIN7

R

E

>G

TC

DREF7

R

E

>G

(001) R

E

>G

R

6

E

>G

(000)

R8

E

>G

DO7

32 TAP CORRELATOR STAGE RO7

MR7

+

R

E

>G

5

TC

CONFIG(4:0)

DATA OUT

RO7

CORRELATION

SCORE OUT

CO7

DO7

DIN6

R

E

>G

CONFIG(4:0)

RO7

DREF6

R

E

>G

DO6

32 TAP CORRELATOR STAGE RO6

MR6

+

R

E

>G

DATA OUT

RO6

CO6

DO1

DIN0

R

E

>G

DREF0

R

E

>G

CONFIG(4:0)

RO1

32 TAP CORRELATOR STAGE

MR0

DO0

RO0

+

R

E

>G

CLK

CASIN(12:0)

OEA

OEC

NOTE: All registers clocked with CLK unless otherwise specified.

CORRELATOR BLOCK DIAGRAM

MUX

ARRAY

5

RO0

CO0

REFERENCE OUT

CASIN(12:0)

OEA

OEC

DOUT(7:0)

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