IDT723612L15PF(1997) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT723612L15PF
(Rev.:1997)

BiCMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT723612 BiCMOS SyncBiFIFO™

64 x 36 x 2

CLKA

CSA

W/RA

tCLK

tCLKH

tCLKL

LOW

LOW

MBA

ENA

LOW

tENS2

tENH2

COMMERCIAL TEMPERATURE RANGE

EFA

A0 - A35

CLKB

FFB

CSB

WRB

MBB

ENB

B0 - B35

HIGH

tA

Previous Word in FIFO2 Output Register

tSKEW1(1)

Next Word From FIFO2

tCLK

tCLKH

tCLKL

1

FIFO2 Full

LOW

HIGH

2

tWFF

tWFF

tENS3

tENS2

tENH3

tENH2

tDS

tDH

To FIFO2

3136 drw 12

Note:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the

next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may

transition HIGH one CLKB cycle later than shown.

Figure 9. FFB Flag Timing and First Available Write when FIFO2 is Full

20

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