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SRIX4K-A3S 데이터 시트보기 (PDF) - STMicroelectronics

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SRIX4K-A3S Datasheet PDF : 5 Pages
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SRIX4K
SUMMARY DESCRIPTION
The SRIX4K is a contactless memory, powered by
an externally transmitted radio wave. It contains a
4096-bit user EEPROM fabricated with STMicro-
electronics CMOS technology. The memory is or-
ganised as 128 blocks of 32 bits. The SRIX4K is
accessed via the 13.56MHz carrier. Incoming data
are demodulated and decoded from the received
Amplitude Shift Keying (ASK) modulation signal
and outgoing data are generated by load variation
using Bit Phase Shift Keying (BPSK) coding of a
847kHz sub-carrier. The received ASK wave is
10% modulated. The Data transfer rate between
the SRIX4K and the reader is 106Kbit/s in both re-
ception and emission modes.
The SRIX4K follows the ISO 14443 part 2 type B
recommendation for the radio-frequency power
and signal interface.
Figure 2. Logic Diagram
SRIX4K
4 Kbit
User
EEPROM
Power
Supply
Regulator
ASK
Demodulator
BPSK
Load
Modulator
AC1
AC0
AI06829
The SRIX4K targets short range applications
which need secure and re-usable products. The
SRIX4K includes an anti-collision mechanism that
allows it to detect and select tags present at the
same time within range of the reader. The anti-col-
lision is based on a probabilistic scanning method
using slot markers. The SRIX4K provides an anti-
clone function which allows its authentication. Us-
ing the STMicroelectronics single chip coupler,
CRX14, it is easy to design a reader with the au-
thentication capability and to build a system with a
high level of security.
Table 1. Signal Names
AC1
Antenna Coil
AC0
Antenna Coil
The SRIX4K contactless EEPROM can be ran-
domly read and write in block mode. Each block is
composed by 32 bits. It offers a set of 10 com-
mands:
s READ_BLOCK
s WRITE_BLOCK
s INITIATE
s PCALL16
s SLOT_MARKER
s SELECT
s COMPLETION
s RESET_TO_INVENTORY
s AUTHENTICATE
s GET_UID
The SRIX4K memory is organized in three areas,
as described in Figure 3. The first area is a reset-
table OTP (one time programmable) area in which
bits can only be switched from 1 to 0. Using a spe-
cial command, it is possible to erase all bits of this
area to 1. The second area provides two 32-bit bi-
nary counters which can only be decremented
from FFFFFFFFh to 00000000h, and gives a ca-
pacity of 4,294,967,296 units per counter. The last
area is the EEPROM memory. It is accessible by
block of 32 bits and includes an auto-erase cycle
during each WRITE_BLOCK command.
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