SPLC782A 데이터 시트보기 (PDF) - Unspecified
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SPLC782A Datasheet PDF : 40 Pages
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SPLC782A
4. SIGNAL DESCRIPTIONS
Mnemonic
PIN No.
Type
Description
VDD
19, 20, 28
I
Logic Power input
VSS
11, 12, 37
I
Ground
VPP
V2
V3
23, 24
22
21
I
LCD Voltage; VLCD = VPP - VSS
I
LCD Bias Voltage Control.
Open for 1/5 Bias, Short for 1/4 Bias
E
27
I
It is a start signal to read data or write data.
R/W
26
l RS
25
entia DB3 - DB0
fid DB7 - DB4
e SEG80 - SEG1
s COM16 - COM9
on U COM8 - COM1
TYPE
32 - 29
36 - 33
46 - 125
45 - 38
1-8
14
s C ER DIRC
15
nplu MIN SHL
16
Su RT MOD1
18
For PA MOD0
17
I
It is a signal to select read or write.
1: Read, 0: Write.
I
It is a signal to select register.
1: Data register (for read and write)
0: Instruction register (for write),
Busy flag -- address counter (for read).
I/O
Low-order 4 data bits
I/O
High-order 4 data bits
O
Segment signals for LCD.
O
Common signals for LCD.
O
Common signals for LCD.
I
LCD Alternate Signals.
TYPE = 0: Type-A
TYPE = 1: Type-B
I
Common Scan Direction
DIRC = 0: COM1 COM2 … COM15 COM16
DIRC = 1: COM16 COM15 … COM2 COM1
I
Segment Shift Direction
SHL = 0: SEG1 SEG2 … SEG79 SEG80
SHL = 1: SEG80 SEG79 … SEG2 SEG1
I
CGROM / CGRAM Mode Select
MOD1
MOD0
Function
1
1
$00 - $0F as CGRAM
1
0
$00 - $07 as CGRAM, $08 - $0F as CGROM
0
1
$00 - $03 as CGRAM, $04 - $0F as CGROM
0
0
$00 - $0F as CGROM
Only
OSC1
CL2
D
13
For internal clock operation, leave this pin open.
For external clock operation, the clock is input to OSC1.
10
O
Test Mode Clock Output; Open for normally use.
9
O
Test Mode Data Output; Open for normally use.
© Sunplus Technology Co., Ltd.
5
Proprietary & Confidential
FEB. 15, 2005
Version: 1.7
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