SP8402 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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SP8402 Datasheet PDF : 6 Pages
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SP8402
Very Low Phase Noise Divider by 2N
The SP8402 is a very low phase noise divider which
divides by powers of two. The S0, S1, S2 data inputs select
the division ratio in the range 21 to 28. Special circuits
techniques have been used to reduce the phase noise
considerably below that produced by standard dividers. The
data inputs are CMOS or TTL compatible.
The SP8402 is packaged in a 28 pin plastic SO package
to be compatible with the SP8400 and SP8401 devices.
FEATURES
I Very low Phase Noise (Typically -155 to 160dBc/Hz at
1kHz offset)
I Supply Voltage 5V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Output Current
Storage Temperature Range
Maximum Clock Input Voltage
6.5V
20mA
-55°C to +125°C
2.5V p-p
Ordering Information
September 2005
SP8402/KG/MPES 28 Pin SOIC Tubes
SP8402/KG/MPFP 28 Pin SOIC* Tubes
SP8402/KG/MP1T 28 Pin SOIC Tape & Reel
*Pb Free Matte Tin
N/C
1
N/C
2
N/C
3
VCC +5V
4
GND
5
CLOCK INPUT
6
CLOCK INPUT
7
CLOCK INPUT
8
CLOCK INPUT
9
GND
10
VCC +5V
11
VCC +5V
12
N/C
13
S0
14
28
N/C
27
N/C
26
N/C
25
N/C
24
N/C
23
N/C
22
N/C
21
OUTPUT
20
OUTPUT
19
N/C
18
VCC +5V
17
N/C
16
S2
15
S1
MP28
Fig.1 Pin connections - top view
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
Frequency (Hz)
Fig.2 Typical single sideband phase noise measured at 768MHz
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1994-2005, Zarlink Semiconductor Inc. All Rights Reserved.
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