5962-92059 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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5962-92059

ADVANCE INFORMATION

Zarlink Semiconductor Inc 

OPERATING NOTES

1. The clock inputs (pins 1 and 2) can be driven single ended or

differentially and should be capacitively coupled to the signal

source. The input signal path is completed by connecting a

capacitor from the internal bias decoupling, pin 3, to ground.

2. In the absence of a signal the device will self-oscillate. If this is

undesirable, it may be prevented by connecting a 15kΩ resistor

from the unused input to VEE. This will reduce the input sensitivity

by approximately 100mV.

SP8602/4

3. The circuit will operate down to DC but slew rate must be better

than 100V/µs.

4. The outputs are compatible with ECLII. There is an internal load

of 4kΩ on each output. The outputs can be interfaced to ECL10K

by the addition of 1·5kΩpulldown resistors from the outputs to VEE

to increase output voltage swing.

5. Input impedance is a function of frequency, See Fig. 4.

6. All components should be suitable for the frequency in use.

TO SAMPLING

SCOPE

FROM GENERATOR

INPUT 1

FROM GENERATOR

INPUT 2

TO SAMPLING

SCOPE

20

33

33

1n

1n

3

2

5

6

450 10n

1n

DUT

1

7

450 10n

33

33

8

3·5k 3·5k

TO SAMPLING

SCOPE

20

VEE

1n

Fig. 5 Test circuit

1n

INPUT

1

15k

1n

440

2

5

DIVIDE BY

440

2

BIAS

4k 4k

8

1n

6

ECL OUTPUT

7

1·5k 1·5k

VEE

Fig. 6 Typical application showing interfacing

3

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