SP8790ACM 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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SP8790ACM Datasheet PDF : 7 Pages
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SP8790
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
Supply voltage, VCC = 5V ±0·25V, VEE = 0V
Temperature, TAMB = 255°C to 1125°C (A Grade), 230°C to 170°C (B Grade)
Characteristic
Value
Symbol
Units
Min. Max.
Conditions
Notes
Maximum frequency (sinewave input)
Power supply current
Control input high voltage
Control input low voltage
Output high voltage (pin 3)
Output low voltage (pins 3)
Output high voltage (pin 2)
Output low voltage (pin 2)
Clock to counter output 2ve going delay
Clock to counter output 1ve going delay
Clock to control output 2ve going delay
Clock to control output 1ve going delay
Control input to control output 2ve going delay
Control input to control output 1ve going delay
fMAX
60
MHz Tested as a controller, see Fig. 4 2
ICC
11 mA
2
VINH 3·5 10 V
2
VINL
0 1·5 V
2
VOH
9
V Pin 3 via 1·6kΩ to110V
2
VOL
0·4 V Pin 3 via 1·6kΩ to110V
2
VOH 4·27 4·5 V VCC = 5·2V (25°C)
VOL 3·28 3·7 V VCC = 5·2V (25°C)
tpHL
25 ns
3
tpLH
40 ns
3
tpHL
15 ns 10kΩ pull-down on control output 3, 4
tpLH
26 ns 10kΩ pull-down on control output 3, 4
tpHL
12 ns 10kΩ pull-down on control output 3, 4
tpLH
16 ns 10kΩ pull-down on control output 3, 4
NOTES
1. The test configuration for dynamic testing is shown in Fig.4.
2. Tested at low and high temperatures only.
3. Guaranteed but not tested.
4. The propagation delays stated are with the device controlling the SP8695, which has internal 10kΩpull-down resistors on its PE inputs. These
propagation delays will be reduced when the device is used with the SP8643/47 and SP8740 series of 2-modulus dividers, which have internal
4·3kΩ pull-downs. Refer to relevant data sheet/s.
CLOCK INPUT
CONTROL INPUT
COUNTER OUTPUT (PIN 3)
CONTROL OUTPUT (PIN 2)
N.B: IF CONTROL INPUT = ‘1’ THEN CONTROL OUTPUT = ‘1’
Fig. 3 Timing diagram
OPERATING NOTES
1. The device will normally be driven by capacitively coupling
the inputs to the outputs of a 2-modulus divider, as shown in
Figs. 4 and 5. The maximum frequency of the device when
used as a controller is limited by the internal delays to 60MHz.
However, when used as a 44 prescaler, it will operate at
frequencies in excess of 80MHz, the maximum frequency
being limited by saturation of the output stage.
2. The device is normally driven from very fast edges of a 2-
modulus divider, in which case there is no input slew rate
problem.
3. The control input is TTL/CMOS compatible.
2
4. The counter output (pin 3) interfaces to TTL/CMOS by the
addition of a pull-up resistor. For interfacing to CMOS, the
output can be connected with a pull-up resistor to a supply
which must not exceed 12V.
5. When used as a controller the device will self-oscillate in the
absence of an input signal; this can be prevented by connecting
a 47kΩ resistor from pin 7 to ground, as shown in Fig. 5.
6. The control output, which includes an internal 16kΩ pull-
down resistor, is ECL compatible and will interface directly to
ECL 2-modulus dividers such as the GPS SP8600 and SP8700
series as shown in Figs. 4 and 5.
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