U62H64SA35LG1 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
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U62H64SA35LG1 Datasheet PDF : 9 Pages
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U62H64
Block Diagram
A6
A7
A8
A9
A10
A11
A12
A0
A1
A2
A3
A4
A5
E2
E1
Address
Change
Detector
Memory Cell
Array
128 Rows
64 x 8 Columns
Sense Amplifier/
Write Control Logic
Clock
Generator
VCC VSS
WG
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Truth Table
Operating Mode
Standby/not selected
Internal Read
Read
* H or L
Write
E1
E2
W
G
*
L
*
*
H
*
*
*
L
H
H
H
L
H
H
L
L
H
L
*
DQ0 - DQ7
High-Z
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
2
April 20, 2004
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