Z87L10 데이터 시트보기 (PDF) - Zilog

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Z87L10

AUDIO ENCODER/DECODERS

Zilog 

Z87010/Z87L10

Audio Encoder/Decoders

AC TIMING DIAGRAMS (Continued)

CK

Interrupt

TINS

TINL

HALT

THS

THH

Figure 7. Interrupt/HALT Timing

Table 3. CODEC Interface-AC Timing

Internal SCLK

Min

SDCR SCLK down from CLK rise

–

SUCR SCLK up from CLK rise

–

FDCR FS0, FS1 down from SCLK rise

–

FUCR FS0, FS1 up from SCLK rise

–

TDSR TXD down from SCLK rise

–

TUSR TXD up from SCLK rise

–

RSU RXD Setup time in respect to

7

SCLK fall

RH

RXD Hold time in respect to

0

SCLK fall

FDCR FS0,FS1 down from SCLK rise

–

FUCR FS0, FS1 up from SCLK rise

–

TDSR TXD down from SCLK rise

–

TUSR TXD up from SCLK rise

–

RSU RXD setup time in respect to

1

SCLK fall

RH

RXD Hold Time in respect to

6

SCLK fall

Zilog

Max

15

15

6

6

7

7

13

13

12

12

2-12

PRELIMINARY

DS96WRL0601

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