AK4544 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AK4544 Datasheet PDF : 35 Pages
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[ASAHI KASEI]
[AK4544A]
Switching Characteristics
Ta=25°C, AVdd=5.0V±5%, DVdd=3.3V±5% or 5V±5%, 50pF external load
Parameter
Symbol
Min
Typ
max
Units
Master Clock Frequency Note)
If Crystal is not used.
Fmclk
-
24.576
-
MHz
45
50
55
%
AC link Interface Timing
BIT_CLK frequency
Fbclk
12.288
MHz
BIT_CLK clock Period(Tbclk=1/Fbclk)
Tbclk
-
81.38
ns
BIT_BLK low pulse width
Tclk_low
36
40.7
45
ns
BIT_BLK low pulse width
Tclk_high
36
40.7
45
ns
BIT_CLK rise time
Trise_clk
-
-
6
ns
BIT_CLK fall time
Tfall_clk
-
-
6
ns
SYNC frequency
-
48
-
kHz
SYNC low pulse width
SYNC high pulse width
SYNC rise time
SYNC fall time
Setup time(SYNC, SDATA_OUT)
Hold time(SYNC, SDATA_OUT)
SDATA_IN delay time from BIT_CLK
rising edge
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Tsync_low
Tsync_high
Trise_sync
Tfall_sync
Tsetup
Thold
Tdelay
Trise_din
Tfall_din
Trise_dout
Tfall_dout
-
19.5
-
(240 cycle)
-
1.3
-
(16 cycle)
-
-
6
-
-
6
10
-
-
25
-
-
-
-
15
-
-
6
-
-
6
-
-
6
-
-
6
µs
(Tbclk)
µs
(Tbclk)
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cold Rest (SDATA_OUT=L, SYNC=L)
RESET# active low pulse width
Trst_low
1.0
-
RESET# inactive to BIT_CLK delay
Trst2clk
162.8
(2 cycle)
-
µs
ns
(Tbclk)
Warm Rest Timing
SYNC active low pulse width
SYNC inactive to BIT_CLK delay
Tsync_high
1.0
1.3
-
µs
(16 cycle)
(Tbclk)
Tsync2clk
162.8
ns
(2 cycle)
(Tbclk)
AC-link Low Power Mode Timing
End of Slot 2 to BIT_CLK, SDATA_IN
Ts2_pdwn
-
Low
-
1.0
µs
Activate Test Mode Timing
Setup to trailing edge of RESET#
Hold from RESET# rising edge
Rising edge of RESET# to Hi-Z
Falling edge of RESET# to “L”
Tsetup2rst
15.0
-
Thold2rst
100
-
Toff
-
-
Tlow
-
-
-
ns
-
ns
50
ns
50
ns
Note ) The use of a crystal is recommended. If master clock is supplied from controller (or if a external oscillator is
used), Master Clock should be input to XTAL_IN, meanwhile XTAL_OUT should be open.
<MS0026-E-00>
-7-
2000/04
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