YMF753 데이터 시트보기 (PDF) - Yamaha Corporation
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YMF753 Datasheet PDF : 26 Pages
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YMF753
SYSTEM CONNECTION DIAGRAM
Mono Out
L-ch LNLVL Out
R-ch LNLVL Out
L-ch LINE Out
R-ch LINE Out
PC Beep
Phone
L-ch AUX
R-ch AUX
L-ch Video
R-ch Video
L-ch CD
CD Ground
R-ch CD
MIC
L-ch Line IN
R-ch Line IN
PC_BEEP
PHONE
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
LINE_IN_L
LINE_IN_R
MIC2
YMF753-S
SDATA IN
SDATA OUT
BIT CLK
SYNC
RESET#
Vref
Vrefout
MSEL
AVdd1,2
AVss1,2
DVdd1,2
DVss1,2
XTL_OUT
XTL_IN
ZV BCK
ZV SIN
ZV LR
EAPD / DIT
+5.0V
+3.3V
DGND AGND
1) Power and Ground
To get the most out of analog performance, it is necessary to split the ground into analog and digital blocks.
Analog ground and digital ground earth at one point closed to the initial ground supply of the board. The
layout of the ground pattern should be designed as large as possible and the impudence should be reduced to
prevent from receiving ambient noise. In addition, use 0.1µF and 47µF capacitors to connect between the
analog voltage pin and the analog ground as well as between the digital supply pin and the digital ground.
2) Reference Voltage
As the reference voltage determines all analog signals’ reference levels of YMF753, noise generated from
the reference voltage could affect the YMF753’s analog performance. To stabilize the YMF753’s reference
voltage, insert a 0.1µF ceramic capacitor in parallel with a 22µF capacitor between Vref pin and the ground.
The 0.1µF ceramic capacitor should be designed as close to the Vref pin as possible
3) Master Clock
To suppress the master clock from affecting its surroundings, it is recommended to keep the master clock
guarded on the ground so the noise can be reduced.
4) Unused Analog Input / Output pins
For the unused analog input pins, short them through a 0.1µF ceramic capacitor to the analog ground. For
the unused analog output pins, they should be left opened.
16
March 6, 2001
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