SN74LS299DW 데이터 시트보기 (PDF) - ON Semiconductor

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SN74LS299DW

8-Bit Shift/Storage Register with 3-State Outputs

ON Semiconductor 

S1 19 S0 1

SN74LS299

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC S1 Ds7 Q7 I/O7 I/O5 I/O3 I/O1 CP DS0

20 19 18 17 16 15 14 13 12 11

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual InĆLine Package.

1 2 3 4 5 6 7 8 9 10

S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND

PIN NAMES

CP

DS0

DS7

I/On

OE1, OE2

Q0, Q7

MR

S0, S1

Clock Pulse (Active Positive-Going Edge) Input

Serial Data Input for Right Shift

Serial Data Input for Left Shift

Parallel Data Input or

Parallel Output (3-State)

3-State Output Enable (Active LOW) Inputs

Serial Outputs

Asynchronous Master Reset (Active LOW) Input

Mode Select Inputs

NOTES:

ąa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

65 U.L.

0.5 U.L.

10 U.L.

0.5 U.L.

1 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

15 U.L.

0.25 U.L.

5 U.L.

0.25 U.L.

0.5 U.L.

LOGIC DIAGRAM

DS0

11

12

CLOCK

Q0 8

MR 9

OE1 2

OE2 3

18

DS7

DC

CLRQK

7

I/O0

DC

CLRQK

DC

CLRQK

13

I/O1

6

I/O2

DC

CLRQK

14

I/O3

DC

CLRQK

5

I/O4

DC

CLRQK

DC

CLRQK

15

4

I/O5

I/O6

DC

CLRQK

17

Q7

16

I/O7

VCC = PIN 20

GND = PIN 10

= PIN NUMBERS

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