SN74LS194 데이터 시트보기 (PDF) - ON Semiconductor

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SN74LS194

LOW POWER SCHOTTKY

ON Semiconductor 

SN74LS194A

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC Q0 Q1 Q2 Q3 CP S1 S0

16 15 14 13 12 11 10 9

1 2 3 4 56 78

MR DSR P0 P1 P2 P3 DSL GND

PIN NAMES

S0, S1

P0 – P3

DSR

DSL

CP

MR

Q0 – Q3

Mode Control Inputs

Parallel Data Inputs

Serial (Shift Right) Data Input

Serial (Shift Left) Data Input

Clock (Active HIGH Going Edge) Input

Master Reset (Active LOW) Input

Parallel Outputs

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

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