HC6094 데이터 시트보기 (PDF) - Intersil

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HC6094

ADSL Analog Front End Chip

Intersil 

HC6094

Shift Register Format

Each write operation to a control register involves 16 bits of the rising edge of SCLK. A3-A0 supply the address of the

data. The CS- signal must be enabled low during any serial control register, and D7-D0 supply the data.

write operation. The data on SDI shall be clocked in during

CS-

SCLK

SDI

0 A0 A1 A2 A3 0 0 0 D0 D1 D2 D3 D4 D5 D6 D7

FIGURE 1. SERIAL CONTROL

Logic Timing Definitions

CS

SCLK

t2

t1

t4

SCLK

SDI

t3

t5

FIGURE 2. SERIAL INTERFACE

CLK

DAC DATA

tS tH

FIGURE 3. DAC INTERFACE

6

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