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MC14LC5540DW 데이터 시트보기 (PDF) - Motorola => Freescale

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MC14LC5540DW
Motorola
Motorola => Freescale Motorola
MC14LC5540DW Datasheet PDF : 18 Pages
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PIN DESCRIPTIONS
POWER SUPPLY PINS
VSS
Negative Power Supply
(PDIP, SOG—Pin 22; TQFP—Pin 21)
This is the most negative power supply and is typically
connected to 0 V.
VEXT
External Power Supply Input
(PDIP, SOG—Pin 9; TQFP—Pin 7)
This power supply input pin must be between 2.70 and
5.25 V. Internally, it is connected to the input of the VDSP
voltage regulator, the 5 V regulated charge pump, and all
digital I/O including the Serial Control Port and the ADPCM
Serial Data Port. This pin is also connected to the analog out-
put drivers (PO+, PO–, AXO+, and AXO–). This pin should
be decoupled to VSS with a 0.1 µF ceramic capacitor. This
pin is internally connected to the VDD and VDSP pins when
the device is powered down.
VDSP
Digital Signal Processor Power Supply Output
(PDIP, SOG—Pin 8; TQFP—Pin 5)
This pin is connected to the output of the on–chip VDSP
voltage regulator which supplies the positive voltage to the
DSP circuitry and to the other digital blocks of the ADPCM
Codec. This pin should be decoupled to VSS with a 0.1 µF
ceramic capacitor. This pin cannot be used for powering
external loads. This pin is internally connected to the VEXT
pin during power–down to retain memory.
VDD
Positive Power Supply Input/Output
(PDIP, SOG, TQFP—Pin 28)
This is the positive output of the on–chip voltage regulated
charge pump and the positive power supply input to the ana-
log sections of the device. Depending on the supply voltage
available, this pin can function in one of two different oper-
ating modes:
1. When VEXT is supplied from a regulated 5 V (± 5%)
power supply, VDD is an input and should be externally
connected to VEXT. Charge pump capacitor C1 should
not be used and the charge pump should be disabled in
BR0 (b2). In this case VEXT and VDD can share the same
0.1 µF ceramic decoupling capacitor to VSS.
2. When VEXT is supplied from 2.70 to 5.25 V, such as
battery powered applications, the charge pump should
be used. In this case, VDD is the output of the on–chip
voltage regulated charge pump and must not be con-
nected to VEXT. VDD should be decoupled to VSS with a
1.0 µF ceramic capacitor. This pin cannot be used for
powering external loads in this operating mode. This pin
is internally connected to the VEXT pin when the charge
pump is turned off or the device is powered down.
VAG
Analog Ground Output
(PDIP, SOG—Pin 4; TQFP—Pin 32)
This output pin provides a mid–supply analog ground reg-
ulated to 2.4 V. All analog signal processing within this device
is referenced to this pin. This pin should be decoupled to VSS
with a 0.01 µF ceramic capacitor. If the audio signals to be
processed are referenced to VSS, then special precautions
must be utilized to avoid noise between VSS and the VAG pin.
Refer to the applications information in this document for
more information. The VAG pin becomes high impedance
when in analog power–down mode.
C1–, C1+
Charge Pump Capacitor Pins
(PDIP, SOG, TQFP—Pins 23 and 24)
These are the capacitor connections to the internal voltage
regulated charge pump that generates the VDD supply volt-
age. A 0.1 µF capacitor should be placed between these
pins. Note that if an external VDD is supplied, this capacitor
should not be in the circuit.
ANALOG INTERFACE PINS
TG
Transmit Gain
(PDIP, SOG—Pin 1; TQFP—Pin 29)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 kload to the VAG pin.
When TI– and TI+ are connected to VDD, the TG op amp is
powered down and the TG pin becomes a high–impedance
input to the transmit filter. All signals at this pin are refer-
enced to the VAG pin. This pin is high impedance when the
device is in the analog power–down mode. This op amp is
powered by the VDD pin.
TI–
Transmit Analog Input (Inverting)
(PDIP, SOG—Pin 2; TQFP—Pin 30)
This is the inverting input of the transmit gain setting op-
erational amplifier. Gain setting resistors are usually con-
nected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.0 V, to VDD – 2 V. Connecting this pin and TI +
to VDD will place this amplifier’s output (TG) in a high–imped-
ance state, thus allowing the TG pin to serve as a high–im-
pedance input to the transmit filter.
TI+
Transmit Analog Input (Non–Inverting)
(PDIP, SOG—Pin 3; TQFP—Pin 31)
This is the non–inverting input of the transmit input gain
setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the VSS
pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already refer-
enced to the VAG pin. The common mode range of the TI+
and TI– pins is from 1.0 V to VDD – 2 V. Connecting this pin
and TI– to VDD will place this amplifier’s output (TG) in a
MOTOROLA
MC14LC5540
3

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