MC14LC5540DW 데이터 시트보기 (PDF) - Motorola => Freescale

부품명

상세내역

일치하는 목록

MC14LC5540DW

ADPCM Codec

Motorola => Freescale 

is controlled in BR7 (b5). If the FST enable goes low before

the falling edge of BCLKT during the last bit of the ADPCM

word, the digital data output circuitry counts BCLKT cycles to

keep the data output (DT pin) low impedance for the duration

of the ADPCM data word (2, 3, 4, or 8 BCLKT cycles) minus

one half of a BCLKT cycle.

Receive Digital

The receive digital section of this device accepts serial

ADPCM (PCM) words at the DR pin under the control of the

BCLKR and FSR pins. The FSR enable duration, measured

in BCLKR cycles, tells the device which decode algorithm

(i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM)

the DSP machine should use for the word that is being re-

ceived at the DR pin. This algorithm may be changed on a

frame by frame basis.

The DSP machine receives an interrupt when an ADPCM

word has been received and is waiting to be decoded into a

PCM word. The DSP machine performs a decode and an

encode every frame when the device is operating in its full

duplex conversation mode. The DSP machine decodes the

ADPCM word according to CCITT G.726 for 32 kbps,

24 kbps, and 16 kbps. This decoding includes the correction

for the CCITT/ANSI Sync function, except when the receive

digital gain is used. The receive digital gain is anticipated to

be user adjustable gain control in handset applications

where as much as 12 dB of gain or more than 12 dB of atten-

uation may be desirable. The receive digital gain is a linear

multiply performed on the 13–bit linear data before it is con-

verted to Mu–Law or A–Law, and is programmed via the SCP

port in BR3 (b7:b0). The decoded PCM word may be read via

the SCP port in BR10 (b7:b0).

Receive Analog Signal Processing

The receive analog signal processing section includes the

DAC described above, a sample and hold amplifier, a trim

gain stage, a 5–pole, 3400 Hz switched capacitor low–pass

filter with sinX/X correction, and a 2–pole active smoothing

filter to reduce the spectral components of the switched ca-

pacitor filter. (The receive low–pass smoothing filter may be

removed from the signal path for the additional spectral com-

ponents for applications using the on–chip tone generator

function described below. This low–pass filter performs the

sinX/X compensation. The receive filter is removed from the

circuit via the SCP in BR2 (b4).) The input to the smoothing

filter is the output to the receive trim gain stage. This stage is

intended to compensate for gain tolerances of external com-

ponents such as handset receivers. This stage is capable of

0 to 7 dB of attenuation in 1–dB steps. This stage only ac-

commodates attenuation because the nominal signal levels

of the DAC should be next to the clip levels of this device’s

circuitry and any positive gain would overdrive the outputs.

The gain is programmed via the SCP port in BR2 (b2:b0).The

output of the 2–pole active smoothing filter is buffered by an

amplifier which is output at the RO pin. This output is capable

of driving a 2 kΩ load to the VAG pin.

Receive Analog Output Drivers and Power Supply

The high current analog output circuitry (PO+, PO–, PI,

AXO+, AXO–) is powered by the VEXT power supply pin. Due

to the wide range of VEXT operating voltages for this device,

this circuitry and the RO pin have a programmable reference

MC14LC5540

12

point of either VAG (2.4 V) or VEXT/2. In applications where

this device is powered with 5 V, it is recommended that the dc

reference for this circuitry be programmed to VAG. This

allows maximum output signals for driving high power tele-

phone line transformer interfaces and loud speaker/ringers.

For applications that are battery powered, VAG pin will still be

2.4 V, but the receive analog output circuitry will be powered

from as low as 2.7 V. To optimize the output power, this cir-

cuitry should be referenced to one half of the battery voltage,

VEXT/2. The RO pin is powered by the VDD pin, but its dc

reference point is programmed the same as the high current

analog output circuitry.

This device has two pairs of power amplifiers that are con-

nected in a push–pull configuration. These push–pull power

driver pairs have similar drive capabilities, but have different

circuit configurations and different intended uses. The PO+

and PO– power drivers are intended to accommodate large

gain ranges with precise adjustment by two external resistors

for applications such as driving a telephone line or a handset

receiver. The PI pin is the inverting input to the PO– power

amplifier. The non–inverting input is internally tied to the

same reference as the RO output. This allows this amplifier

to be used in an inverting gain circuit with two external resis-

tors. The PO+ amplifier has a gain of – 1, and is internally

connected to the PO– output. This complete power amplifier

circuit is a differential (push–pull) amplifier with adjustable

gain which is capable of driving a 300 Ω load to + 12 dBm

when VEXT is 5 V. The PO+ and PO– outputs are intended

to drive loads differentially and not to VSS or VAG. The PO+

and PO– power amplifiers may be powered down indepen-

dently of the rest of the chip by connecting the PI pin to VDD

or in BR2 (b5).

The other paired power driver outputs are the AXO+ and

AXO– Auxiliary outputs. These push–pull output amplifiers

are intended to drive a ringer or loud speaker with imped-

ance as low as 300 Ω to + 12 dBm when VEXT is 5 V. The

AXO+ and AXO– outputs are intended to drive loads dif-

ferentially and not to VSS or VAG. The AXO+ and AXO–

power amplifiers may be powered down independently of the

rest of the chip via the SCP port in BR2 (b6).

SIDETONE

The Sidetone function of this device allows a controlled

amount of the output from the transmit filter to be summed

with the output of the DAC at the input to the receive low–

pass filter. The sidetone component has gains of –8.5 dB,

v –10.5 dB, –12.0 dB, –13.5 dB, –15.0 dB, –18.0 dB,

–21.5 dB, and – 70 dB. The sidetone function is controlled

by the SCP port in BR1 (b6:b4).

UNIVERSAL TONE GENERATOR

The Universal Dual Tone Generator function supports both

the transmit and the receive sides of this device. When the

tone generator is being used, the decoder function of the

DSP circuit is disabled. The output of the tone generator is

made available to the input of the receive digital gain function

for use at the receive analog outputs. In handset applica-

tions, this could be used for generating DTMF, distinctive

ringing or call progress feedback signals. In telephone line

interface applications, this tone generator could be used for

signaling on the line. The tone generator output is also

available for the input to the encoder function of the DSP

machine for outputting at the DT pin. This function is useful in

MOTOROLA

Share Link: