UT62W1024-70(2003) 데이터 시트보기 (PDF) - Utron Technology Inc
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UT62W1024-70 Datasheet PDF : 15 Pages
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UTRON
Rev. 1.1
UT62W1024
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 10µA (typical) L-version
1µA (typical) LL-version
Wide range power supply : 2.7V to 5.5V
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20mm TSOP-1
32-pin 8x13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
A0-A16
Vcc
Vss
DECODER
1024 X 1024
MEMORY
ARRAY
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE
CE2
OE
W
E
CONTROL
CIRCUIT
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE ,CE2
WE
OE
VCC
VSS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
GENERAL DESCRIPTION
The UT62W1024 is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62W1024 is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT62W1024 operates from a wide range of
2.7V~ 5.5V power supply and all inputs and outputs
are fully TTL compatible.
PIN CONFIGURATION
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
Vss
16
32
Vcc
31
A15
30
CE2
29
WE
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
PDIP / SOP
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 UT62W1024 25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
TSOP-I/STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
P80056
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