UT62L1024PCL-70LE 데이터 시트보기 (PDF) - Utron Technology Inc
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UT62L1024PCL-70LE Datasheet PDF : 17 Pages
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UTRON
Rev. 1.9
UT62L1024
128KX8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN
-
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX.
6
8
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.4V to 2.4V
5ns
1.5V
CL=50pF, IOH/IOL=-1mA/2mA
AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA = 0℃ to +70℃/-20℃ to +80℃(E))
(1) READ CYCLE
PARAMETER
SYMBOL
Read Cycle Time
tRC
Address Access Time
tAA
Chip Enable Access Time
tACE
Output Enable Access Time
tOE
Chip Enable to Output in Low-Z tCLZ*
Output Enable to Output in Low-Z tOLZ*
Chip Disable to Output in High-Z tCHZ*
Output Disable to Output in High-Z tOHZ*
Output Hold from Address Change tOH
UT62L1024-35
MIN. MAX.
35
-
-
35
-
35
-
25
10
-
5
-
-
25
-
25
5
-
UT62L1024-55
MIN. MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
30
-
30
5
-
UT62L1024-70
MIN. MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
35
-
35
5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62L1024-35 UT62L1024-55
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC
35
-
55
-
Address Valid to End of Write
tAW
30
-
50
-
Chip Enable to End of Write
tCW
30
-
50
-
Address Set-up Time
tAS
0
-
0
-
Write Pulse Width
tWP
25
-
40
-
Write Recovery Time
tWR
0
-
0
-
Data to Write Time Overlap
tDW
20
-
25
-
Data Hold from End of Write-Time tDH
0
-
0
-
Output Active from End of Write tOW*
5
-
5
-
Write to Output in High-Z
tWHZ*
-
15
-
20
*These parameters are guaranteed by device characterization, but not production tested.
UT62L1024-70
MIN. MAX.
70
-
60
-
60
-
0
-
45
-
0
-
30
-
0
-
5
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P80033
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